clash-ghc VS logisim-evolution

> You'd be better off with a higher-level or more modern HDL that compiles to Verilog/VHDL. "Chisel" is one such.

As is Clash :) https://clash-lang.org/

You can take a look at https://clash-lang.org/. There is also a book for it. https://gergo.erdi.hu/retroclash/

I don't know much about FPGAs, but Clash lang compiles to VHDL, and might do the trick: https://clash-lang.org

if you need inspiration there is a full UART core available in clash: https://github.com/clash-lang/clash-compiler/blob/master/clash-cores/src/Clash/Cores/UART.hs

Perhaps peripheral (the original site has been hugged to death).

Both clashlang: https://clash-lang.org/

And Hardcaml: https://github.com/janestreet/hardcaml

have personally fueled my interest in hardware.

Dan Luu speaks eloquently and at length about how better options are needed for logic design. I would recommend both of the above to the enthusiastic novice.

I have downloaded logisim-evolution from github. While trying to run .msi file, Microsoft Defender blocked it for some reason. I scanned it with some other scanners and everything was fine. I'm not sure if this is safe to install it.

I am trying to define an xbps-src template for logisim-evolution, a Java app that requires Java 16. I am using depends="virtual?java-runtime" and, as expected by reading etc/defaults.virtual, OpenJDK 8 is used. Creating a etc/virtual file is ignored in .gitignore, so I guess it is made to be used with local packages. Using depends="virtual?java-runtime-17.0.5+7_1" works, as OpenJDK 17 provides that exact version of java-runtime. If it were updated, this package would break, because if I input a lower version, it will fail. I've tried using syntax like > and >=, but then I get the following error:

Logism evolution works great and is quite modern.

https://github.com/logisim-evolution/logisim-evolution

According to Logisim it creates the correct sequence for full stepping on a bipolar configuration. Falstad's Circuit simulator is another one you might try.

Did you check logisim-evolution? It is an active fork of logisim maintained by several lecturers at the Bern University of Applied Sciences.

Here is the link for Logisim Evolution: https://github.com/logisim-evolution/logisim-evolution

In school, I worked on an introductory CS/EE class many, many moons ago, and I believed we used something like "logisim", which by then was pretty awesome - you could build simple things like adders, combine those with "macros" to bui;d ALUs and then whole simple CPUs.

Since then, the logisim project has discontinued, but it looks like there is a open source successor:

https://github.com/logisim-evolution/logisim-evolution

Have not tried it, but it looks promising, provided you don't want to do too complicated things (not sure if you could really model complex CPUs like a pentium with it). Also, it's pretty digital only, so I wouldn't expect Mac-Spice-like analog circuit simulation.

though i'd heavily recommend first building the circuit in a logic simulator like Logisim, or Digital before trying to build it in a game for an FPGA. (Digital even allows you to export circuits as Verilog/VHDL, and as a certified lazy person, that is very useful)

Logisim-evolution An alternative free and open-source tool to design and simulate digital logic.

See if you are comfortable playing in https://github.com/logisim-evolution/logisim-evolution