clash-ghc
hardcaml
clash-ghc | hardcaml | |
---|---|---|
33 | 7 | |
1,375 | 613 | |
0.9% | 0.8% | |
9.1 | 6.4 | |
2 days ago | 7 days ago | |
Haskell | OCaml | |
GNU General Public License v3.0 or later | MIT License |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
clash-ghc
- Clash: A Functional Hardware Description Language
- Clash (Haskell) for ASIC design
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Building a Networked Key-Value-Store on an FPGA
> You'd be better off with a higher-level or more modern HDL that compiles to Verilog/VHDL. "Chisel" is one such.
As is Clash :) https://clash-lang.org/
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Need project idea
You can take a look at https://clash-lang.org/. There is also a book for it. https://gergo.erdi.hu/retroclash/
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5 layered CNN implementation on arduino/FPGAs [P]
I don't know much about FPGAs, but Clash lang compiles to VHDL, and might do the trick: https://clash-lang.org
- An addressable little explored language gap: HDL - Hardware Description Languages, any language used for electronic circuit design, description, and specs
- Pedagogical Downsides of Haskell
- Ask HN: Choice of HDL for an FPGA Project
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Baud rate 1.5% lower than expected, is this normal?
if you need inspiration there is a full UART core available in clash: https://github.com/clash-lang/clash-compiler/blob/master/clash-cores/src/Clash/Cores/UART.hs
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A circuit simulator that doesn't look like it was made in 2003
Perhaps peripheral (the original site has been hugged to death).
Both clashlang: https://clash-lang.org/
And Hardcaml: https://github.com/janestreet/hardcaml
have personally fueled my interest in hardware.
Dan Luu speaks eloquently and at length about how better options are needed for logic design. I would recommend both of the above to the enthusiastic novice.
hardcaml
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Zero Knowledge FPGAs
title: Accelerating zk-SNARKs - MSM and NTT algorithms on FPGAs with Hardcaml
Any reason the title deviates so much from original? Is it because of all the cool acronyms and code words? Here's a decoder:
zk-SNARK: zero-knowledge Succinct Non-Interactive Argument of Knowledge
MSM: Multi-Scalar Multiplication
Hardcaml: OCaml lib for hardware: https://github.com/janestreet/hardcaml
NTT: Number Theoretic Transform
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A circuit simulator that doesn't look like it was made in 2003
Perhaps peripheral (the original site has been hugged to death).
Both clashlang: https://clash-lang.org/
And Hardcaml: https://github.com/janestreet/hardcaml
have personally fueled my interest in hardware.
Dan Luu speaks eloquently and at length about how better options are needed for logic design. I would recommend both of the above to the enthusiastic novice.
- Functional programming language for embedded devices?
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HRT or Jane Street?
Join JS and you can program FPGAs in a strongly typed, expressive, high level programming language (OCaml): https://github.com/janestreet/hardcaml
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You need to stop idolizing programming languages.
[1] https://github.com/janestreet/hardcaml
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Designing a MIPS CPU in Hardcaml (12 part series)
> You can put all the functions/tasks you want in that module.
Coming from a software background, the testing strategies available in Verilog seem very clunky and overly verbose. In comparison, Hardcaml's ASCII waveform expect-test solution feels extremely elegant and simple: https://blog.janestreet.com/using-ascii-waveforms-to-test-ha....
> And all of my development and that of my team happens through gitlab-CI.
That's probably more of a gap in my education than a fault of the ecosystem then.
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Among other qualities, I prefer languages that let fewer mistakes slip through, and allow the developer to focus on the system they intend to build rather than avoiding bugs/misunderstandings that would be easy to catch otherwise. You bring up a lot of really good points, and I suspect that if we were doing Verilog "the right way", we would have probably run into fewer issues. But at the end of the day, developing in Hardcaml was a much more ergonomic experience: testing was straightforward, most "stupid mistakes" were impossible, setup was pretty easy, and the library provided a lot of really useful abstractions. For example, Hardcaml interfaces make it easy to represent practically any data structure that can be serialized to/from a bit vector, and the Always API allows for some pretty interesting non-trivial functional logic.
https://github.com/janestreet/hardcaml/blob/master/docs/hard...
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Hardcaml MIPS CPU Learning Project and Blog
A few months ago, I came across the Signals and Threads Programmable Hardware episode. I really liked the idea of Hardcaml: a library to write and test hardware designs in OCaml. Representing circuits as functions felt like a good abstraction, and I’ve been wanting to learn OCaml for a while.
What are some alternatives?
wiringPi - A Haskell binding to the wiringPi library, for using GPIO on the Raspberry Pi.
bitvec - A crate for managing memory bit by bit
clash-prelude
bap - Binary Analysis Platform
mercury-api - Haskell binding to Mercury API for ThingMagic RFID readers
nerves_system_osd32mp1 - Base system for Octavo OSD32MP1
ICFP2020_Bluespec_Tutorial - Tutorial on hardware design using Bluespec BH (Bluespec Classic) for Haskell programmers at ACM ICFP 2020 conference
nerves - Craft and deploy bulletproof embedded software in Elixir
riscv-cores-list - RISC-V Cores, SoC platforms and SoCs
qucs_s - Qucs-S is a circuit simulation program with Qt-based GUI
amaranth - A modern hardware definition language and toolchain based on Python
logisim-evolution - Digital logic design tool and simulator