hardcaml
bitvec
hardcaml | bitvec | |
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7 | 17 | |
613 | 1,138 | |
0.8% | 0.4% | |
6.4 | 0.0 | |
7 days ago | 13 days ago | |
OCaml | Rust | |
MIT License | MIT License |
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hardcaml
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Zero Knowledge FPGAs
title: Accelerating zk-SNARKs - MSM and NTT algorithms on FPGAs with Hardcaml
Any reason the title deviates so much from original? Is it because of all the cool acronyms and code words? Here's a decoder:
zk-SNARK: zero-knowledge Succinct Non-Interactive Argument of Knowledge
MSM: Multi-Scalar Multiplication
Hardcaml: OCaml lib for hardware: https://github.com/janestreet/hardcaml
NTT: Number Theoretic Transform
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A circuit simulator that doesn't look like it was made in 2003
Perhaps peripheral (the original site has been hugged to death).
Both clashlang: https://clash-lang.org/
And Hardcaml: https://github.com/janestreet/hardcaml
have personally fueled my interest in hardware.
Dan Luu speaks eloquently and at length about how better options are needed for logic design. I would recommend both of the above to the enthusiastic novice.
- Functional programming language for embedded devices?
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HRT or Jane Street?
Join JS and you can program FPGAs in a strongly typed, expressive, high level programming language (OCaml): https://github.com/janestreet/hardcaml
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You need to stop idolizing programming languages.
[1] https://github.com/janestreet/hardcaml
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Designing a MIPS CPU in Hardcaml (12 part series)
> You can put all the functions/tasks you want in that module.
Coming from a software background, the testing strategies available in Verilog seem very clunky and overly verbose. In comparison, Hardcaml's ASCII waveform expect-test solution feels extremely elegant and simple: https://blog.janestreet.com/using-ascii-waveforms-to-test-ha....
> And all of my development and that of my team happens through gitlab-CI.
That's probably more of a gap in my education than a fault of the ecosystem then.
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Among other qualities, I prefer languages that let fewer mistakes slip through, and allow the developer to focus on the system they intend to build rather than avoiding bugs/misunderstandings that would be easy to catch otherwise. You bring up a lot of really good points, and I suspect that if we were doing Verilog "the right way", we would have probably run into fewer issues. But at the end of the day, developing in Hardcaml was a much more ergonomic experience: testing was straightforward, most "stupid mistakes" were impossible, setup was pretty easy, and the library provided a lot of really useful abstractions. For example, Hardcaml interfaces make it easy to represent practically any data structure that can be serialized to/from a bit vector, and the Always API allows for some pretty interesting non-trivial functional logic.
https://github.com/janestreet/hardcaml/blob/master/docs/hard...
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Hardcaml MIPS CPU Learning Project and Blog
A few months ago, I came across the Signals and Threads Programmable Hardware episode. I really liked the idea of Hardcaml: a library to write and test hardware designs in OCaml. Representing circuits as functions felt like a good abstraction, and I’ve been wanting to learn OCaml for a while.
bitvec
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bitcode 0.4 release - binary serialization format
I was also under the false impression that bitwise encoding was slow. When I first implemented bitcode with bitvec I got performance 20x worse than bincode. After writing my own implementation I was able to get much better performance.
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An optimized replacement of the infamous std::vector<🅱️ool>
interesting; i'll have to compare this to my rust counterpart. your numbers indicate some clever implementations i'd love to read
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You need to stop idolizing programming languages.
Not to mention having a lackluster std which causes you to use nonstardard not so well documented crates and a 40K LoC library to do "bit-twiddling" (the lib, https://github.com/bitvecto-rs/bitvec the blog that says "twiddle bits" https://blog.adamchalmers.com/making-a-dns-client/ and for crying out loud the blogger also used the language the author mentioned and I quote "ergonomics AND speed AND correctness")
- bit-twiddling tricks. It's the perfect example of Rust's no-compromises "ergonomics AND speed AND correctness" ideals
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An Armful of CHERIs: Memory Safety in the processor. Do we still need safe languages with CHERI?
https://github.com/bitvecto-rs/bitvec/issues/135 is a very funny read about how to perform inttoptr with provenance retention
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bitvec 1.0.0 Released
Technically #135 gives me license to yank affected crates, but since the only exploit is "Miri crashes exactly one test out of the suite" it's not really worth it to be a stickler. Call it a truce
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What are some creative/advanced uses of macro_rules?
My friend Nika wrote a macro that packs a sequence of 1, 0, … tokens into a correctly structured bit-buffer, adaptable over any register type or bit-ordering, at compile time. It's now basically this whole file
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Where do I document a published crate?
if you are interested in a user manual, you can use mdbook as well. for an example, my bitvec project uses mdbook (book.toml) and a github action (.github/workflows/gh-pages.yml) to compile the guide and host it as a github pages website. it's slightly more complicated, and i'd like docs.rs to follow hexdoc.pm's example of hosting both api docs and prose, but until then this is a pretty reasonable solution.
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Idiomatic Way to Validate Struct Field Values
the first one
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When and how to use traits?
i would browse the standard library, tower, nom, or my own bitvec to see layout and trait/record separation. in particular, std::io and std::net may be of use: io::Read and io::Write are pervasive examples of implementing unixy file-descriptor-like behavior in the type system
What are some alternatives?
bap - Binary Analysis Platform
nom - Rust parser combinator framework
nerves_system_osd32mp1 - Base system for Octavo OSD32MP1
rfcs - RFCs for changes to Rust
nerves - Craft and deploy bulletproof embedded software in Elixir
time - The most used Rust library for date and time handling.
qucs_s - Qucs-S is a circuit simulation program with Qt-based GUI
byteorder - Rust library for reading/writing numbers in big-endian and little-endian.
clash-ghc - Haskell to VHDL/Verilog/SystemVerilog compiler
tower - async fn(Request) -> Result<Response, Error>
logisim-evolution - Digital logic design tool and simulator
alacritty - A cross-platform, OpenGL terminal emulator.