clash-calculator
lion
| clash-calculator | lion | |
|---|---|---|
| 1 | 10 | |
| 1 | 242 | |
| - | 0.0% | |
| 1.8 | 4.5 | |
| over 2 years ago | 6 days ago | |
| Haskell | Haskell | |
| MIT License | BSD 3-clause "New" or "Revised" License |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
clash-calculator
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Trouble setting up Nix for Retrocomputing with Clash example code
I'm reading through Retrocomputing with Clash. The example projects use stack to build. I'm trying to use iohk's haskell.nix with it. For the one example project clash-calculator, when I run nix develop and it builds clash-ghc I get the following warning
lion
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A year of RISC-V adventures: embracing chaos in your software journey [video]
I've been starting to dabble with digital logic design via Clash (https://clash-lang.org/), and there is a very cool-looking RISC-V SoC project done in that tool that looks fairly serious: https://github.com/standardsemiconductor/lion.
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C++ Concurrency Model on x86 for Dummies
That’s fascinating about the M1. In retrospect it seems like kind of a no-brainer but I doubt I would have thought of it.
SPARC had different memory models at different ISA revs IIRC: it’s been like 20 years since I was dealing with SPARC so I might be misremembering the details. Alpha would have been a better example.
RISC-V is really interesting. I’ve been slowly working through this: https://github.com/standardsemiconductor/lion, highly recommend!
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Why More Networks Should Imitate Cardano When It Comes To Writing And Shipping Code | Bitcoinist.com
Interesting. Actually, you may be just the person to answer my question: Is it possible/plausible to run a Cardano node on Lion OS on a RISC-V machine? IMO, it would be great for the community if we could run all Cardano stake pools on end to end formally verified machines using open source core and hardware.
- Lion is a formally verified, 5-stage pipeline RISC-V core
- Lion: A formally verified, 5-stage pipeline RISC-V core
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Hacker News top posts: Mar 4, 2021
Lion: A formally verified, 5-stage pipeline RISC-V core\ (30 comments)
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Where Lions Roam: RISC-V on the VELDT
In addition, you can actually set the riscv-formal suite to verify correctness by k-induction: https://github.com/SymbioticEDA/riscv-formal/pull/28 https://symbiyosys.readthedocs.io/en/latest/quickstart.html#beyond-bounded-model-checks although I concur that by looking at https://github.com/standardsemiconductor/lion/blob/main/lion-formal/app/Main.hs the lion core is only verified with BMC.
What are some alternatives?
retroclash-lib - Library code for upcoming RetroClash book
prometheus-cpp - Prometheus Client Library for Modern C++
clash-compucolor2 - Clash implementation of the Compucolor II home computer
riscv-formal - RISC-V Formal Verification Framework
clash-pong - Pong in Haskell / Clash, running as software using SDL and as hardware targeting FPGAs
cocotb - cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
atomic-story - Understanding how atomics and memory ordering work
VexRiscv - A FPGA friendly 32 bit RISC-V CPU implementation
libcxx - Project moved to: https://github.com/llvm/llvm-project
wit - WIT (Wikipedia-based Image Text) Dataset is a large multimodal multilingual dataset comprising 37M+ image-text sets with 11M+ unique images across 100+ languages.
VELDT-getting-started - Where Lions Roam: Haskell & Hardware on VELDT
iele-semantics - Semantics of Virtual Machine for IELE prototype blockchain