chisel
pyright
chisel | pyright | |
---|---|---|
25 | 135 | |
3,717 | 12,098 | |
1.1% | 1.8% | |
9.7 | 9.8 | |
7 days ago | 1 day ago | |
Scala | Python | |
Apache License 2.0 | GNU General Public License v3.0 or later |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
chisel
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Calyx: Intermediate Language for Hardware Accelerators
My first instinct was to ask "Does this play well with CIRCT?" And thankfully they answer that right away in the README.
I'm personally of the opinion that there is a LOT of room for improvement in the hardware design tooling space, but a combination of market consolidation, huge pressure to meet deadlines, and an existing functional pipeline of Verilog/VHDL talent is preventing changes.
That's not to say "Verilog/VHDL are bad", because clearly they've been good enough to support nearly all of the wonderful designs powering today's devices. But it is to say, "the startup scene for hardware will continue to look anemic compared to the SaaS scene until someone gives me all of the niceties I have for building SaaS tools in software."
A huge amount of ideas (and entire designs) start off as software sims, which enables kernel/compiler engineers to start building out support for new hardware before it's manufactured.
There is some interesting work going on at SiFive building hardware with Chisel[1], as well as some interesting work lead by a professor at William and Mary to improve simulations[2].
1: https://www.chisel-lang.org
2: https://github.com/sarchlab/akita
- Chisel: A Modern Hardware Design Language
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I may be creating an abomination
Inspired by Scala. Which can do a whole lot more, and worse. The currently biggest competitor to decades old hardware description languages is a Scala DSL.
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An addressable little explored language gap: HDL - Hardware Description Languages, any language used for electronic circuit design, description, and specs
Already mentioned Chisel: https://www.chisel-lang.org/
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Trying to learn and work with FPGAs
I'm also a hobbyist. There are a number of alternative HDLs out there, and as hobbyists we can deviate more from the mainstream of (System)Verilog and VHDL if we desire, though you'll still need to be able to read them. In the past I've done Verilog, but lately I've been using SpinalHDL and have been really enjoying it. Its close relative Chisel also makes appearances in the RISC-V space.
- Alternate HDL language and Physical Design/EDA tools?
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Learning VDHL after knowing Verilog
What are your thoughts on other HDLs like Chisel or BlueSpec when it comes to better type checking?
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Learning Verilog and FPGA
I started playing with FPGAs and HDLs a couple years ago with no hardware design background (I'm mostly a software architect/engineer) and in the end found that a "higher-level" HDL suited me better.
I chose Chisel (https://www.chisel-lang.org/) an HDL based on Scala (technically a Scala DSL) which can provide many facilities to hardware generation.
I'd highly advise looking into it although also knowing Verilog helps a lot.
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If you keep clicking "Give 15 seconds" on Lichess, eventually it overflows to a negative number and you win
But some go further and ask "what if when we add a soldering station on top of it?"
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What universities have good PhD programmes in digital design?
In recent years Chisel HDL, RISC V, and SiFive came out of their architecture group, to name a few.
pyright
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Enhance Your Project Quality with These Top Python Libraries
Pyright is a fast type checker meant for large Python source bases. It can run in a “watch” mode and performs fast incremental updates when files are modified.
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How to speed up Pyright + eglot.
However, I made it faster for my use-case by changing some settings. Neovim allows to have these settings in the setup function for LSP. I was trying to figure out how do I change these settings with doom emacs. Pyright docs suggest to have these settings in pyrightconfig.json.
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Mypy 1.6 Released
Not exactly what you are looking for but maybe useful to others.
https://github.com/microsoft/pyright/blob/main/docs/mypy-com...
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VSCodium – Libre Open Source Software Binaries of VS Code
You can use pyright instead[0]. It is the FOSS version of pyright, but having some features missing.
[0]: https://github.com/microsoft/pyright
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How do you enable semantic highlighting for Python?
Unfortunately, pyright explicitly stated that they are not interested in inlay hints or other language server features, that those will only be added to pylance. That's why I added it myself instead of submitting a pull request to pyright. See https://github.com/microsoft/pyright/issues/4325
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How do I enable an LSP for json files?
return { -- add pyright to lspconfig { "neovim/nvim-lspconfig", ---@class PluginLspOpts opts = { ---@type lspconfig.options servers = { -- Listed servers will be automatically loaded to buffers jsonls = { settings = { json = { format = { enable = true, }, }, validate = { enable = true }, }, }, pyright = { settings = { python = { analysis = { -- https://github.com/microsoft/pyright/blob/main/docs/settings.md autoSearchPaths = false, useLibraryCodeForTypes = true, diagnosticMode = "openFilesOnly", }, }, }, }, }, -- Add folding capability to use LSP for ufo plugin capabilities = { textDocument = { foldingRange = { dynamicRegistration = false, lineFoldingOnly = true, }, }, }, }, }, }
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VSCode isn't Recognizing installed Python Modules?
[{ "resource": "/Documents/Coding/VSCode/Projects/Photoeditor/PhotoEditor.py", "owner": "_generated_diagnostic_collection_name_#0", "code": { "value": "reportMissingModuleSource", "target": { "$mid": 1, "external": "https://github.com/microsoft/pyright/blob/main/docs/configuration.md#reportMissingModuleSource", "path": "/microsoft/pyright/blob/main/docs/configuration.md", "scheme": "https", "authority": "github.com", "fragment": "reportMissingModuleSource" } }, "severity": 4, "message": "Import \"requests\" could not be resolved from source", "source": "Pylance", "startLineNumber": 2, "startColumn": 8, "endLineNumber": 2, "endColumn": 16 }]
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Pyright does not respect virtualenv (astronvim)
I don't use astro, but you can configure pyright by using a pyrightconfig.json or directly in the LSP configuration.
- Eglot + pyright can not get completion on django.db.models
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Remote Development, Python IDE.
I prefer jedi over pyright as pyright has crippled documentation support outside of VSCode. I also found jedi is make correct suggestions based on inferred type in some situations where pyright would need type annotation to provide completions, pyright is significantly faster though. Jedi with mypy and flake8 is comparable to pyright I think, but unfortunately mypy wasn't working over tramp. Also isort wasn't working over tramp, but jedi, black, importmagic and flake8 all worked.
What are some alternatives?
SpinalHDL - Scala based HDL
jedi-language-server - A Python language server exclusively for Jedi. If Jedi supports it well, this language server should too.
myhdl - The MyHDL development repository
mypy - Optional static typing for Python
amaranth - A modern hardware definition language and toolchain based on Python
python-lsp-server - Fork of the python-language-server project, maintained by the Spyder IDE team and the community
cocotb - cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
python-language-server - Microsoft Language Server for Python
skywater-pdk - Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.
coc-jedi - coc.nvim wrapper for https://github.com/pappasam/jedi-language-server
bsc - Bluespec Compiler (BSC)
pylance-release - Documentation and issues for Pylance