charbel
PipelineC
| charbel | PipelineC | |
|---|---|---|
| 2 | 46 | |
| 18 | 544 | |
| - | - | |
| 1.2 | 9.5 | |
| about 1 year ago | 3 days ago | |
| Clojure | Python | |
| MIT License | GNU General Public License v3.0 only |
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charbel
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Verilog Is Weird
SV and VHDL are nasty languages, but as you said, they are "industry standard". Chisel and Haskell-based approaches are better but virtually nobody adopts them.
I tried to go in another direction, to make design code shorter by using Clojure syntax. The result is here: https://github.com/m1kal/charbel and works for simple modules. I don't expect wide adoption, but we need to look for new directions instead of sticking to the methods and languages from the 80s.
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Charbel - write synthesizable FPGA code with Clojure syntax
Source: https://github.com/m1kal/charbel (includes simple examples)
PipelineC
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PipelineC Example: FM Radio Demodulation (FPGA SDR)
Related: PipelineC: A C-like hardware description language (HDL):
https://github.com/JulianKemmerer/PipelineC
- Generate non-CPU FPGA circuits from a C-like language
- What makes C, Verilog, Java, Python, etc. so different?
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What are your private FPGA projects and why?
https://github.com/JulianKemmerer/PipelineC :)
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What's the right path to learning for someone coming from software?
However, I think its still possible to have a productive C->HDL journey. Check out PipelineC, https://github.com/JulianKemmerer/PipelineC, its meant for folks with C experience to get right into doing RTL style reasoning :)
- Seeking Advice on How to approch RTL Programming
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Using FPGAs for computations as a beginner
https://github.com/JulianKemmerer/PipelineC-Graphics/blob/main/doc/Sphery-vs-Shapes.pdf https://github.com/JulianKemmerer/PipelineC
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Generating pipeline stages automatically?
This is exactly what the PipelineC tool was made for. https://github.com/JulianKemmerer/PipelineC
- Does Xilinx use multiplication algorithms to speed up/reduce the multipliers size?
- Sphery vs. Shapes, the first raytraced game that is not software
What are some alternatives?
bsc - Bluespec Compiler (BSC)
pygears - HW Design: A Functional Approach
cocotb - cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
pycparser - :snake: Complete C99 parser in pure Python
nngen - NNgen: A Fully-Customizable Hardware Synthesis Compiler for Deep Neural Network
hls4ml - Machine learning on FPGAs using HLS
antikernel - The Antikernel operating system project
Silice - Silice is an easy-to-learn, powerful hardware description language, that simplifies designing hardware algorithms with parallelism and pipelines.
basejump_stl - BaseJump STL: A Standard Template Library for SystemVerilog
hVHDL_example_project - An example project which uses many of the ideas and features of the hVHDL libraries like fixed and floating point math modules and has build scripts for most common FPGAs
DFHDL - DFiant HDL (DFHDL): A Dataflow Hardware Descripition Language