caf_verilog
By chiranthsiddappa
dspfilters
A collection of demonstration digital filters (by ZipCPU)
| caf_verilog | dspfilters | |
|---|---|---|
| 1 | 2 | |
| 1 | 128 | |
| - | - | |
| 9.4 | 3.5 | |
| 8 days ago | 4 months ago | |
| Python | Verilog | |
| MIT License | - |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
caf_verilog
Posts with mentions or reviews of caf_verilog.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2022-11-24.
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Looking to implimenting an autocorrelation function (ACF) into one of my projects.
- You can find the ACF used in the paper with the link from the citations here: https://github.com/chiranthsiddappa/caf_verilog/blob/main/caf_verilog/xcorr.py
dspfilters
Posts with mentions or reviews of dspfilters.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2022-11-24.
-
Looking to implimenting an autocorrelation function (ACF) into one of my projects.
Have you considered this article? It goes over the basics of the autocorrelation function, while also illustrating how you can build one with a Wishbone interface. Further, the Verilator logic for this function is kept and maintained on github here. Sure, it uses Wishbone. If you want to use AXI you can either use a bridge, or rework the the interface (it's not that hard ...).
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Professional or Hobby?
I marked as "both" above, but one might argue that my "hobby" designs are more "Internal Research and Development" (IR&D) than just hobby. Everything has a purpose. Today's hobby design may be used in tomorrow's paying project. Examples include the both the ZipCPU and its subcomponents, my AXI work, DSP filters, PLLs, FFT and much more--all of which have found their way into a variety of customer designs.
What are some alternatives?
When comparing caf_verilog and dspfilters you can also consider the following projects:
wb2axip - Bus bridges and other odds and ends
cordic - A series of CORDIC related projects
vgasim - A Video display simulator
dpll.v
dblclkfft
dpll - A collection of phase locked loop (PLL) related projects