basic-ecp5-pcb
hdl
| basic-ecp5-pcb | hdl | |
|---|---|---|
| 1 | 5 | |
| 85 | 1,378 | |
| - | 2.0% | |
| 0.0 | 9.1 | |
| almost 3 years ago | 8 days ago | |
| Verilog | Verilog | |
| Creative Commons Zero v1.0 Universal | GNU General Public License v3.0 or later |
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basic-ecp5-pcb
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Power IC for ECP5
See e.g. https://github.com/mattvenn/basic-ecp5-pcb
hdl
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Timing diagram help
Have you thought about using ADs source code and pulling what you need to create a front end to their device?
- Vivado 2020.2 IP Repository Suggestion
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Anyone else feeling extremely frustrated with Xilinx?
The reference designs from Analog Devices are all hand coded complex block designs for both Intel and Xilinx: https://github.com/analogdevicesinc/hdl
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Intel Quartus Version Control?
There’s 100 million ways people skin this cat. Some people guard this like it’s fort know. ADI publishes theirs on GitHub in adi_hdl that supports both vivado and quartus. https://github.com/analogdevicesinc/hdl
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Industry development process?
I haven't used this repo, but something like this https://github.com/analogdevicesinc/hdl/tree/master/library
What are some alternatives?
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NTHU-ICLAB - 清華大學 | 積體電路設計實驗 (IC LAB) | 110上
corundum - Open source FPGA-based NIC and platform for in-network compute
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clash-pong - Pong in Haskell / Clash, running as software using SDL and as hardware targeting FPGAs
FPGA_SDRAM_Controller - SDRAM controller optimized to a memory bandwidth of 316MB/s