basejump_stl
BaseJump STL: A Standard Template Library for SystemVerilog (by bespoke-silicon-group)
fusesoc-cores
FuseSoC standard core library (by fusesoc)
| basejump_stl | fusesoc-cores | |
|---|---|---|
| 4 | 1 | |
| 447 | 97 | |
| 2.0% | - | |
| 6.2 | 4.5 | |
| about 1 month ago | 6 months ago | |
| SystemVerilog | ||
| GNU General Public License v3.0 or later | - |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
basejump_stl
Posts with mentions or reviews of basejump_stl.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2022-01-20.
-
Extra-wide aspect ratio FIFO in Vivado?
BaseJump STL ( https://github.com/bespoke-silicon-group/basejump_stl ) has lots of these plumbing modules, silicon-validated several times
-
Cross module reference (XMR)?
It depends on your mapping algorithm and whether the tools you’re looking at supported mixed-language synthesis, but you can always use our battle-tested components for these kind of functions: https://github.com/bespoke-silicon-group/basejump_stl
-
Any recommendations for an RTL "standard library"?
https://github.com/bespoke-silicon-group/basejump_stl maybe?
- Data flow ternary vs behavioral case statements
fusesoc-cores
Posts with mentions or reviews of fusesoc-cores.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2021-11-18.
What are some alternatives?
When comparing basejump_stl and fusesoc-cores you can also consider the following projects:
chisel - Chisel: A Modern Hardware Design Language
opentitan - OpenTitan: Open source silicon root of trust
surf - A huge VHDL library for FPGA development
PipelineC - A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.
fusesoc - Package manager and build abstraction tool for FPGA/ASIC development
axi - AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
satcat5 - SatCat5 is a mixed-media Ethernet switch that lets a variety of devices communicate on the same network.
tiny-cores - Collection of assorted small cores