PERCIVAL
Open-Source Posit RISC-V Core with Quire Capability (by artecs-group)
cs2410
An out-of-order execution CPU simulator for CS2410 Computer Architecture course final project at the University of Pittsburgh. (by Jacob-Hoff-man)
PERCIVAL | cs2410 | |
---|---|---|
1 | 1 | |
40 | 3 | |
- | - | |
3.3 | 6.5 | |
8 months ago | 11 months ago | |
C++ | C++ | |
GNU General Public License v3.0 or later | - |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
PERCIVAL
Posts with mentions or reviews of PERCIVAL.
We have used some of these posts to build our list of alternatives
and similar projects.
-
[2111.15286] PERCIVAL: Open-Source Posit RISC-V Core with Quire Capability
They implement posit, a floating-point number format, to CVA6. The implementation is published at https://github.com/artecs-group/PERCIVAL
cs2410
Posts with mentions or reviews of cs2410.
We have used some of these posts to build our list of alternatives
and similar projects.
-
Sophie Wilson. She designed the architecture behind your phone’s CPU. She is also a trans woman.
Here is a CPU simulator that I made during the Spring semester, which implements a subset of the RISC V ISA. :)
What are some alternatives?
When comparing PERCIVAL and cs2410 you can also consider the following projects:
qtrvsim - RISC-V CPU simulator for education purposes
gem5 - The official repository for the gem5 computer-system architecture simulator.
ChampSim - ChampSim is an open-source trace based simulator maintained at Texas A&M University and through the support of the computer architecture community.