XiangShan VS thead-extension-spec

Are you calling for the government to pick a winner? The Chinese word for this fierce if at times chaotic competition is "juan". It worked for them in EV and PV. The outcome remains to be seen in chips and commercial space launches. But even their mostly (ex-)students-run open source Xiangshan RiscV project https://github.com/OpenXiangShan/XiangShan shows a remarkable level of sophistication.

> Certainly no RISC-V implementations that are in the hands of customers right now do any fusion and it doesn't seem to hurt their ability to match or exceed the performance of similar Arm cores (A55, A72).

You can play around with OpenXianShan though, they have a few fusion targets: https://github.com/OpenXiangShan/XiangShan/blob/master/src/m...

Most of the targets require the same destination, so it won't be able to fuse current codegen. I suppose there is still some time before compilers need to be ready, but it's not that much.

> Perhaps they will provide compiler patches if required.

I hope so, btw t-head seems to be still be trying to upstream XTheadVector: https://gcc.gnu.org/pipermail/gcc-patches/2024-January/64278...

This is the most advanced open source risc-v implementation I'm awair of: https://github.com/OpenXiangShan/XiangShan

Maybe implement a big feature for a open source design? like vroom or xiangshan.

I did know about XiangShan, but not Aolai. Is it a Linux distribution?

If you are interested in high performance look into vroom , c910 and xianghan, maybe you could adopt one of them.

"Real truth" and "fan boys"? Let's have some facts: there are indeed a boatload of extensions, though perhaps not (yet) to the V extension itself.

T-HEAD [1], Ventana's ternary op [2], Sifive also has a couple [3], including "Xsfvfwmaccqqq", one of at least four completely different matmul variants.

In particular for the latter, I would say fragmentation is an absolutely valid concern at the moment.

[1]: https://github.com/T-head-Semi/thead-extension-spec

TH1520 (and SG2042, D1) have THead custom extension that contains a lot of the same things as Zba and Zbb, just slightly different and with encodings in the custom opcode spaces.

e.g. "th.addsl rd, rs1, rs2, imm2" which has an immediate field for the shift instead of separate instructions (which is just documentation really), and shifts rs2 while Zba's sh1add, sh2add, sh3add shift rs1.

Also th.ff0, th.ff1, th.rev, th.tstnbz (same as orc.b but with inverted result)

They also have pre- and post-increment loads and stores with writeback of the incremented pointer, and [rs1 + rs2 << imm2] loads and stores, which can be useful for JITing x86 (or ARM) addressing modes.

https://github.com/T-head-Semi/thead-extension-spec/releases...