VHDL_real_time_simulation
Simple project for for a blog post with synthesizable models of buck converters (by johonkanen)
pyxsi
Python/C/RTL cosimulation with Xilinx's xsim simulator (by gsmecher)
| VHDL_real_time_simulation | pyxsi | |
|---|---|---|
| 1 | 4 | |
| 0 | 55 | |
| - | - | |
| 4.3 | 4.4 | |
| about 1 year ago | 6 months ago | |
| VHDL | C++ | |
| MIT License | GNU General Public License v3.0 or later |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
VHDL_real_time_simulation
Posts with mentions or reviews of VHDL_real_time_simulation.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2023-05-23.
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Question for those who do DSP/algorithm verification
An example vhdl real time simulation
pyxsi
Posts with mentions or reviews of pyxsi.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2023-05-23.
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Question for those who do DSP/algorithm verification
These three environments are glued together using pyxsi, which embeds Xilinx's simulator kernel (xsim). The result is a complicated monolith, but avoids the following "Bad Practices for Complex Dataflow":
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interaction between vivado simulator and C/C++
Adam mentions it in his Aduvio post, but pyxsi shows how to stack Python on C/C++ on Vivado. (Disclaimer: mine.)
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[CocoTB for beginners]: FPGA/ASIC Testbenches in Python + Automated Testing in GitHub​
The sketch here is a little stale but shows the general idea.
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How good is the Vivado XSI?
I'm trying to understand if we can use the Vivado XSI to make our verification tasks easier and improve our coverage via a more productive language like C++ or python. I found an interesting project (https://github.com/gsmecher/pyxsi) that uses it but I'm still unsure if this is worth investing time on (given how many issues Xilinx tools usually have).
What are some alternatives?
When comparing VHDL_real_time_simulation and pyxsi you can also consider the following projects:
verilog-ethernet - Verilog Ethernet components for FPGA implementation
rohd - The Rapid Open Hardware Development (ROHD) framework is a framework for describing and verifying hardware in the Dart programming language.
cocotbext-axi - AXI interface modules for Cocotb