UPduino-v3.0
bsc
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| UPduino-v3.0 | bsc | |
|---|---|---|
| 5 | 8 | |
| 314 | 879 | |
| 1.0% | 1.5% | |
| 4.4 | 8.4 | |
| 3 months ago | 18 days ago | |
| HTML | Haskell | |
| MIT License | GNU General Public License v3.0 or later |
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UPduino-v3.0
bsc
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Ao486_MiSTer: i486 core for the MiSTer FPGA gaming system
Many companies do just write entire modern SoCs in straight Verilog (maybe with some autogenerated Verilog hacked in there) with no other major organization tools aside from the typical project management stuff. The load-store unit of a modern CPU alone easily exceeds 10k lines of Verilog. It's a similar thing as people who work with kernels—after all, the page table management code in a modern operating system like Linux is absolutely monstrous but still people are able to understand it well enough to be able to make the changes they need and get out.
If you are interested in other languages which hope to make this sort of stuff easier, I'd recommend taking a look at design productivity languages like Chisel and it's associated Chipyard [1], SpinalHDL [2], and Bluespec [3]. Each of these are meant to make defining extremely complex hardware more manageable for humans and there's a lot of interesting work going on right now with each of them.
[1] https://github.com/ucb-bar/chipyard
[2] https://github.com/SpinalHDL/SpinalHDL
[3] https://github.com/B-Lang-org/bsc
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Learning VDHL after knowing Verilog
What are your thoughts on other HDLs like Chisel or BlueSpec when it comes to better type checking?
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Is “x' = f(x)” a programming paradigm?
In a previous project we used Haskell that compiled down to Verilog to design hardware. Think along the lines of BlueSpec or Clash. Haskell would force you to spell out the new state as a function of the old state of the system. This would let us do gate-level simulations of the hardware we designed. Coupled with Haskell's penchant for using primes to mean "the new value of", stuff like x' = f x was very common.
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I'm starting a project to make a Rust-like hardware description language and I need your opinions.
You should look at Bluespec, they are doing some interesting stuff.
- Verilog Is Weird
- Bluespec hardware design language and simulation tools
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MyHDL: Using Python as a hardware description and verification language
And I've been involved in a project that's making heavy use of Bluespec: https://github.com/B-Lang-org/bsc/
Same problem though - you have to transpile it down to Verilog to use it in anything beyond a simulation.
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FPGA dev board that's cheap, simple and supported by OSS toolchain
FPGA Thread: Bluespec SystemVerilog is now completely open source, very nice HDL although quite opinionated.
https://github.com/B-Lang-org/bsc
it's Haskell underneath (https://xkcd.com/356/)
What are some alternatives?
linux-on-litex-vexriscv - Linux on LiteX-VexRiscv
chisel - Chisel: A Modern Hardware Design Language