Rosebud
hashtables
Rosebud | hashtables | |
---|---|---|
2 | 1 | |
31 | 125 | |
- | - | |
0.0 | 1.0 | |
about 1 year ago | 9 months ago | |
Verilog | Haskell | |
MIT License | BSD 3-clause "New" or "Revised" License |
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For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Rosebud
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ASCII Comparison in VHDL
Here is a python script I wrote a while ago that takes a list of strings and generates verilog code for an efficient bit-split string matching implementation: https://github.com/ucsdsysnet/Shire/blob/master/fpga_src/accel/archive/sme/python/sme_rulecompiler.py
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What do think of Chisel HDL? is it worth learning over Verilog/SystemVerilog?
Sure, I suppose trivial code might be somewhat readable. But doing something non-trivial is a different story. For example, this is what spinal HDL generates for vexriscv: https://github.com/ucsdsysnet/Shire/blob/master/fpga_src/lib/Shire/rtl/VexRiscv.v. This isn't exactly readable. There are about 320 _zz_ signals in there that presumably didn't exist in the original scala code.
hashtables
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[ANN] vector-hashtables
[1] https://github.com/gregorycollins/hashtables/issues/49
What are some alternatives?
tensil - Open source machine learning accelerators
Octree - Octree is a shallow tree structure for 3-dimensional points
chisel-book - Digital Design with Chisel
gps2htmlReport - Generates a HTML page report detailing a GPS journey, with charts, statistics and an OpenStreetMap graphic.
discrimination - Fast linear time sorting and discrimination for a large class of data types
unordered-containers - Efficient hashing-based container types
llrbtree - Left-leaning red-black trees
minst-idx - Read and write data in the IDX format used in e.g. the MNIST database
jsons-to-schema - Unifies JSON documents (and JSON Schemas) into a single schema
hebrew-time - Hebrew dates and prayer times.
CTRex - Open records for Haskell
unsafely - Flexible access control for unsafe operations and instances