Rosebud
Framework for FPGA-accelerated Middlebox Development (by ucsdsysnet)
chisel-book
Digital Design with Chisel (by schoeberl)
| Rosebud | chisel-book | |
|---|---|---|
| 2 | 4 | |
| 31 | 699 | |
| - | - | |
| 0.0 | 8.1 | |
| about 1 year ago | 8 days ago | |
| Verilog | TeX | |
| MIT License | - |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Rosebud
Posts with mentions or reviews of Rosebud.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2022-06-29.
-
ASCII Comparison in VHDL
Here is a python script I wrote a while ago that takes a list of strings and generates verilog code for an efficient bit-split string matching implementation: https://github.com/ucsdsysnet/Shire/blob/master/fpga_src/accel/archive/sme/python/sme_rulecompiler.py
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What do think of Chisel HDL? is it worth learning over Verilog/SystemVerilog?
Sure, I suppose trivial code might be somewhat readable. But doing something non-trivial is a different story. For example, this is what spinal HDL generates for vexriscv: https://github.com/ucsdsysnet/Shire/blob/master/fpga_src/lib/Shire/rtl/VexRiscv.v. This isn't exactly readable. There are about 320 _zz_ signals in there that presumably didn't exist in the original scala code.
chisel-book
Posts with mentions or reviews of chisel-book.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2023-01-08.
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Lua on an FPGA
If you do your work in Chisel the creator of JOP also wrote a book on Chisel, then you might be able to get some free advice along the way, :)
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Which you woukd choose between SpinalHDL, Chisel or Clash as begineer?
Chisel likely has the largest user base of these three and should also be the most mature because of this. There is a book to go with it https://github.com/schoeberl/chisel-book.
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What do think of Chisel HDL? is it worth learning over Verilog/SystemVerilog?
Sure. You can follow this little .pdf: https://github.com/schoeberl/chisel-book
- Silice: A language for hardcoding Algorithms into FPGA hardware
What are some alternatives?
When comparing Rosebud and chisel-book you can also consider the following projects:
tensil - Open source machine learning accelerators
Silice - Silice is an easy-to-learn, powerful hardware description language, that simplifies designing hardware algorithms with parallelism and pipelines.
discrimination - Fast linear time sorting and discrimination for a large class of data types
VexRiscv - A FPGA friendly 32 bit RISC-V CPU implementation
hashtables - Mutable hash tables for Haskell, in the ST monad