PyRTL
Pyverilog
PyRTL | Pyverilog | |
---|---|---|
1 | 2 | |
235 | 573 | |
2.6% | 1.4% | |
7.5 | 0.0 | |
16 days ago | 9 months ago | |
Python | Python | |
BSD 3-clause "New" or "Revised" License | Apache License 2.0 |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
PyRTL
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Tools for designing hardware in Python
Any hardware designers here who use Python for designing hardware? There are a bunch of libraries that all seem promising MyHDL, PyRTL, PyVerilog, PyLog, PyMTL3, ... All seem to work roughly the same. Write code in Python and transpile it to VHDL/Verilog. Which of these are popular and well-maintained? MyHDL looks good but it's last release was 0.10 in 2018 and for hardware design you don't want to rely on 0.x software. Anything like Chisel for Python.
Pyverilog
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Tools for designing hardware in Python
Any hardware designers here who use Python for designing hardware? There are a bunch of libraries that all seem promising MyHDL, PyRTL, PyVerilog, PyLog, PyMTL3, ... All seem to work roughly the same. Write code in Python and transpile it to VHDL/Verilog. Which of these are popular and well-maintained? MyHDL looks good but it's last release was 0.10 in 2018 and for hardware design you don't want to rely on 0.x software. Anything like Chisel for Python.
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How to compare HDL simulation/implementation results to Matlab?
PyVerilog https://github.com/PyHDI/Pyverilog
What are some alternatives?
myhdl - The MyHDL development repository
pyverilator - Python wrapper for verilator model
pymtl3 - Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework
pylog - PyLog: An Algorithm-Centric FPGA Programming and Synthesis Flow
datamodel-code-generator - Pydantic model and dataclasses.dataclass generator for easy conversion of JSON, OpenAPI, JSON Schema, and YAML data sources.
PyChip-py-hcl - A Hardware Construct Language
nmigen - A refreshed Python toolbox for building complex digital hardware. See https://gitlab.com/nmigen/nmigen
nngen - NNgen: A Fully-Customizable Hardware Synthesis Compiler for Deep Neural Network
qemu - Xilinx's fork of Quick EMUlator (QEMU) with improved support and modelling for the Xilinx platforms.