PipelineC
CflexHDL
| PipelineC | CflexHDL | |
|---|---|---|
| 46 | 4 | |
| 548 | 160 | |
| - | - | |
| 9.5 | 5.7 | |
| 12 days ago | about 1 year ago | |
| Python | C | |
| GNU General Public License v3.0 only | GNU General Public License v3.0 or later |
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PipelineC
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PipelineC Example: FM Radio Demodulation (FPGA SDR)
Related: PipelineC: A C-like hardware description language (HDL):
https://github.com/JulianKemmerer/PipelineC
- Generate non-CPU FPGA circuits from a C-like language
- What makes C, Verilog, Java, Python, etc. so different?
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What are your private FPGA projects and why?
https://github.com/JulianKemmerer/PipelineC :)
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What's the right path to learning for someone coming from software?
However, I think its still possible to have a productive C->HDL journey. Check out PipelineC, https://github.com/JulianKemmerer/PipelineC, its meant for folks with C experience to get right into doing RTL style reasoning :)
- Seeking Advice on How to approch RTL Programming
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Using FPGAs for computations as a beginner
https://github.com/JulianKemmerer/PipelineC-Graphics/blob/main/doc/Sphery-vs-Shapes.pdf https://github.com/JulianKemmerer/PipelineC
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Generating pipeline stages automatically?
This is exactly what the PipelineC tool was made for. https://github.com/JulianKemmerer/PipelineC
- Does Xilinx use multiplication algorithms to speed up/reduce the multipliers size?
- Sphery vs. Shapes, the first raytraced game that is not software
CflexHDL
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Am I building the fastest logic simulator?
Have you compared memory usage? Have you tried building the same design you're running at 'hundreds of FPS' on Verilator and seeing how it does there? Do you have a measure of complexity you can use so we can judge how big the design really is? What frequency is the simulator hitting? Do you have support for arbitrary bit widths? From a quick look at https://github.com/suarezvictor/CflexHDL/tree/main/demos/vga it seems all signals in that design are 32 bits or less. When you're outside of your native word width (i.e. likely above 64 bits) performance may be reduced.
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Sphery vs. Shapes, the first raytraced game that is not software
It was done with u/absurdfatalism's PipelineC tool and my CFlexHDL C++ parser tool for handling vector and scalar types in fixed and floating point with a clean syntax.
What are some alternatives?
pygears - HW Design: A Functional Approach
PipelineC-Graphics - Graphics demos
cocotb - cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
pycparser - :snake: Complete C99 parser in pure Python
nngen - NNgen: A Fully-Customizable Hardware Synthesis Compiler for Deep Neural Network
hls4ml - Machine learning on FPGAs using HLS
antikernel - The Antikernel operating system project
bsc - Bluespec Compiler (BSC)
Silice - Silice is an easy-to-learn, powerful hardware description language, that simplifies designing hardware algorithms with parallelism and pipelines.
basejump_stl - BaseJump STL: A Standard Template Library for SystemVerilog
hVHDL_example_project - An example project which uses many of the ideas and features of the hVHDL libraries like fixed and floating point math modules and has build scripts for most common FPGAs
DFHDL - DFiant HDL (DFHDL): A Dataflow Hardware Descripition Language