PhobGCC-doc VS verilog-pcie

I used "composite" (actually monochrome) video output software on the RP2040 for an optional feature on the PhobGCC custom gamecube controller motherboard to allow easy calibration, configuration, and high-frequency input recording and graphing.

Pictures of the output here: https://github.com/PhobGCC/PhobGCC-doc/blob/main/For_Users/P...

Ordering instructions here: https://github.com/PhobGCC/PhobGCC-doc/blob/main/For_Makers/Phob2_Ordering_Guide.md

Hard left drift is 99% the smushed hall sensor solder short issue. Get a modder to redo the hall sensor solder joints per the board fixes documentation.

There are definitely regular old potentiometers in a standard gamecube controller stickbox. However, there are open-source PCBs available nowadays that do support Hall-effect sensors.

Configuration document here: https://github.com/PhobGCC/PhobGCC-doc/blob/main/For_Users/Phob_Calibration_Guide_v0.28.md Phob 1 programming guide here: https://github.com/PhobGCC/PhobGCC-doc/blob/main/For_Users/Phob_Programming_Guide.md

The board ordering guide is here.

The ultimate gamecube controller at this point in time would be a fully customized PhobGCC, which is an open source project featuring hall effect sensors and many other amazing features. You could build one yourself or purchase a pre-built one on etsy or maybe the phob discord. https://github.com/PhobGCC/PhobGCC-doc

We will publish complete instructions at https://github.com/PhobGCC/PhobGCC-doc when it is ready.

The GPU uses https://github.com/alexforencich/verilog-pcie + the Xilinx PCIe hard IP core. When using the device-independent DMA engine, that library supports both Xilinx and Intel FPGAs.

Most definitely. Most of my stuff still uses skid buffers, but I have been converting stuff here and there to use FIFOs, and this I think was one of the first ones I did this to: https://github.com/alexforencich/verilog-pcie/blob/master/rtl/dma_client_axis_source.v. The output FIFO is the last ~70 lines or so. This one doesn't really take that much advantage over the half full feedback. I think that's the case for the PCIe write DMA engine, but that's a much more complex module.

For reference, the new DMA interface module with the generic PCIe interface is here, and the shim for Xilinx UltraScale devices is here.

Try https://github.com/alexforencich/verilog-pcie/blob/master/scripts/pcie_set_speed.sh

You need something a bit lower-level to trigger a reset and re-enumeration of the device. I put this script together for that on linux, definitely saves a lot of reboots when the PCIe configuration does not change: https://github.com/alexforencich/verilog-pcie/blob/master/scripts/pcie_hot_reset.sh . If you do change the BAR configuration or other PCIe IP core settings, a reboot is probably necessary.