PeakRDL-ipxact
Import and export IP-XACT XML register models (by SystemRDL)
PeakRDL-uvm
Generate UVM register model from compiled SystemRDL input (by SystemRDL)
PeakRDL-ipxact | PeakRDL-uvm | |
---|---|---|
1 | 1 | |
31 | 45 | |
- | - | |
0.0 | 5.5 | |
about 1 month ago | 3 months ago | |
Python | Python | |
GNU General Public License v3.0 only | GNU General Public License v3.0 only |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
PeakRDL-ipxact
Posts with mentions or reviews of PeakRDL-ipxact.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2022-03-20.
-
PeakRDL-Regblock: A free & open source tool that generates SystemVerilog control & status registers (CSR) from SystemRDL
If you're interested register automation, be sure to check out some of my other projects: * systemrdl-compiler * Compiler front-end for the SystemRDL 2.0 language. Want to generate something yourself from SystemRDL input? No problem - use this language interpreter as your front-end. * PeakRDL-html * Generates dynamic and pretty looking HTML documentation * PeakRDL-ipxact * Import/export IP-XACT XML * PeakRDL-uvm * Generate a UVM register model * And a bunch of other random stuff under my SystemRDL GitHub project.
PeakRDL-uvm
Posts with mentions or reviews of PeakRDL-uvm.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2022-03-20.
-
PeakRDL-Regblock: A free & open source tool that generates SystemVerilog control & status registers (CSR) from SystemRDL
If you're interested register automation, be sure to check out some of my other projects: * systemrdl-compiler * Compiler front-end for the SystemRDL 2.0 language. Want to generate something yourself from SystemRDL input? No problem - use this language interpreter as your front-end. * PeakRDL-html * Generates dynamic and pretty looking HTML documentation * PeakRDL-ipxact * Import/export IP-XACT XML * PeakRDL-uvm * Generate a UVM register model * And a bunch of other random stuff under my SystemRDL GitHub project.
What are some alternatives?
When comparing PeakRDL-ipxact and PeakRDL-uvm you can also consider the following projects:
skywater-pdk - Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.
rggen - Code generation tool for control and status registers
PeakRDL-html - Generate address space documentation HTML from compiled SystemRDL input
systemrdl-compiler - SystemRDL 2.0 language compiler front-end
pygears - HW Design: A Functional Approach
open-register-design-tool - Tool to generate register RTL, models, and docs using SystemRDL or JSpec input