OpenRAM
spydrnet
OpenRAM | spydrnet | |
---|---|---|
1 | 1 | |
750 | 85 | |
2.8% | - | |
9.2 | 6.8 | |
about 2 months ago | 3 months ago | |
Python | Python | |
BSD 3-clause "New" or "Revised" License | BSD 3-clause "New" or "Revised" License |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
OpenRAM
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TSMC 180nm SP SRAM Compiler
Can’t help with ARM access but FYI: https://github.com/VLSIDA/OpenRAM
spydrnet
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Is there a minimal HDL?
Here is a python tool to modify netlist / edit files. https://github.com/byuccl/spydrnet
What are some alternatives?
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