a2i
fpga_torture
| a2i | fpga_torture | |
|---|---|---|
| 3 | 2 | |
| 27 | 25 | |
| - | - | |
| 10.0 | 0.0 | |
| over 1 year ago | over 1 year ago | |
| VHDL | VHDL | |
| GNU General Public License v3.0 or later | BSD 3-clause "New" or "Revised" License |
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a2i
-
Arm wants to charge dramatically more for chip licenses
Yes, there are open core IPs for POWER:
- https://github.com/OpenPOWERFoundation/a2i
- https://github.com/OpenPOWERFoundation/a2o
- https://github.com/antonblanchard/microwatt
- How long until RISC gets adopted for the desktop?
- The A2I core was used as the general purpose processor for BlueGene/Q
fpga_torture
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Testing the FPGA board
For the second test you could use something like this: https://github.com/stnolting/fpga_torture
-
Maximum FPGA resource utilization
FPGA-agnostic utilization / power-supply stress-test (VHDL): https://github.com/stnolting/fpga_torture
What are some alternatives?
a2o - The A2O core was a follow-on to A2I, written in Verilog, and supported a lower thread count than A2I, but higher performance per thread, using out-of-order execution (register renaming, reservation stations, completion buffer) and a store queue. It is now being updated for compliancy and integration into open projects.
neo430 - :computer: A damn small msp430-compatible customizable soft-core microcontroller-like processor system written in platform-independent VHDL.
microwatt - A tiny Open POWER ISA softcore written in VHDL 2008
sidechan - Side channel communication test within an FPGA
spi-fpga - SPI master and SPI slave for FPGA written in VHDL
forth-cpu - A Forth CPU and System on a Chip, based on the J1, written in VHDL
neorv32 - :rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
vunit - VUnit is a unit testing framework for VHDL/SystemVerilog
fpga-fft - A highly optimized streaming FFT core based on Bailey's 4-step large FFT algorithm