NTHU-ICLAB
hdl
| NTHU-ICLAB | hdl | |
|---|---|---|
| 5 | 5 | |
| 34 | 1,383 | |
| - | 2.3% | |
| 6.9 | 9.1 | |
| almost 2 years ago | 6 days ago | |
| Verilog | Verilog | |
| - | GNU General Public License v3.0 or later |
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NTHU-ICLAB
hdl
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Timing diagram help
Have you thought about using ADs source code and pulling what you need to create a front end to their device?
- Vivado 2020.2 IP Repository Suggestion
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Anyone else feeling extremely frustrated with Xilinx?
The reference designs from Analog Devices are all hand coded complex block designs for both Intel and Xilinx: https://github.com/analogdevicesinc/hdl
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Intel Quartus Version Control?
There’s 100 million ways people skin this cat. Some people guard this like it’s fort know. ADI publishes theirs on GitHub in adi_hdl that supports both vivado and quartus. https://github.com/analogdevicesinc/hdl
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Industry development process?
I haven't used this repo, but something like this https://github.com/analogdevicesinc/hdl/tree/master/library
What are some alternatives?
openlane - OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
fusesoc - Package manager and build abstraction tool for FPGA/ASIC development
ICLAB_final - 清華大學 | 積體電路設計實驗(IC LAB) | Final Project
livehd - Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation
open-fpga-verilog-tutorial - Learn how to design digital systems and synthesize them into an FPGA using only opensource tools
zipcpu - A small, light weight, RISC CPU soft core
psram-tang-nano-9k - An open source PSRAM/HyperRAM controller for Sipeed Tang Nano 9K / Gowin GW1NR-LV9QN88PC6/15 FPGA
FPGA_SDRAM_Controller - SDRAM controller optimized to a memory bandwidth of 316MB/s
uhd - The USRP™ Hardware Driver Repository
OpenTimer - A High-performance Timing Analysis Tool for VLSI Systems
f4pga-examples - Example designs showing different ways to use F4PGA toolchains.