FPGA_Asynchronous_FIFO
hdl
| FPGA_Asynchronous_FIFO | hdl | |
|---|---|---|
| 1 | 5 | |
| 10 | 1,383 | |
| - | 2.3% | |
| 0.0 | 9.1 | |
| over 2 years ago | 4 days ago | |
| Verilog | Verilog | |
| MIT License | GNU General Public License v3.0 or later |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
FPGA_Asynchronous_FIFO
hdl
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Timing diagram help
Have you thought about using ADs source code and pulling what you need to create a front end to their device?
- Vivado 2020.2 IP Repository Suggestion
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Anyone else feeling extremely frustrated with Xilinx?
The reference designs from Analog Devices are all hand coded complex block designs for both Intel and Xilinx: https://github.com/analogdevicesinc/hdl
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Intel Quartus Version Control?
There’s 100 million ways people skin this cat. Some people guard this like it’s fort know. ADI publishes theirs on GitHub in adi_hdl that supports both vivado and quartus. https://github.com/analogdevicesinc/hdl
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Industry development process?
I haven't used this repo, but something like this https://github.com/analogdevicesinc/hdl/tree/master/library
What are some alternatives?
zipcpu - A small, light weight, RISC CPU soft core
fusesoc - Package manager and build abstraction tool for FPGA/ASIC development
open-fpga-verilog-tutorial - Learn how to design digital systems and synthesize them into an FPGA using only opensource tools
livehd - Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation
biriscv - 32-bit Superscalar RISC-V CPU
serv - SERV - The SErial RISC-V CPU
NTHU-ICLAB - 清華大學 | 積體電路設計實驗 (IC LAB) | 110上
darkriscv - opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
psram-tang-nano-9k - An open source PSRAM/HyperRAM controller for Sipeed Tang Nano 9K / Gowin GW1NR-LV9QN88PC6/15 FPGA
FPGA_SDRAM_Controller - SDRAM controller optimized to a memory bandwidth of 316MB/s
uhd - The USRP™ Hardware Driver Repository