Degate
naja-verilog
Degate | naja-verilog | |
---|---|---|
2 | 2 | |
230 | 21 | |
3.0% | - | |
5.7 | 7.6 | |
3 months ago | about 2 months ago | |
C++ | C++ | |
GNU General Public License v3.0 only | Apache License 2.0 |
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Degate
naja-verilog
-
Naja-Verilog: stand-alone structural (gate-level) parser
Hi everyone, If you need to build C++ (or Python) application loading gate level verilog, similar to the one at the input of FPGA PnR tools, https://github.com/xtofalex/naja-verilog is available. This parser has been designed to allow the construction on the fly of any netlist data structure. One note: if you need also a C++ netlist data structure (with Python bindings) to build netlist analysis or editing tools on top, Naja SNL: https://github.com/xtofalex/naja is also ready for use. Hope this is useful. If it is or if you face any issue, please reach to me. Feedback welcome.
- Show HN: Naja-Verilog – Structural Verilog Parser
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