bsc
ao486_MiSTer
bsc | ao486_MiSTer | |
---|---|---|
8 | 21 | |
880 | 236 | |
1.0% | 0.4% | |
8.4 | 5.8 | |
25 days ago | 6 days ago | |
Haskell | Verilog | |
GNU General Public License v3.0 or later | GNU General Public License v3.0 or later |
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bsc
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Ao486_MiSTer: i486 core for the MiSTer FPGA gaming system
Many companies do just write entire modern SoCs in straight Verilog (maybe with some autogenerated Verilog hacked in there) with no other major organization tools aside from the typical project management stuff. The load-store unit of a modern CPU alone easily exceeds 10k lines of Verilog. It's a similar thing as people who work with kernels—after all, the page table management code in a modern operating system like Linux is absolutely monstrous but still people are able to understand it well enough to be able to make the changes they need and get out.
If you are interested in other languages which hope to make this sort of stuff easier, I'd recommend taking a look at design productivity languages like Chisel and it's associated Chipyard [1], SpinalHDL [2], and Bluespec [3]. Each of these are meant to make defining extremely complex hardware more manageable for humans and there's a lot of interesting work going on right now with each of them.
[1] https://github.com/ucb-bar/chipyard
[2] https://github.com/SpinalHDL/SpinalHDL
[3] https://github.com/B-Lang-org/bsc
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Learning VDHL after knowing Verilog
What are your thoughts on other HDLs like Chisel or BlueSpec when it comes to better type checking?
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Is “x' = f(x)” a programming paradigm?
In a previous project we used Haskell that compiled down to Verilog to design hardware. Think along the lines of BlueSpec or Clash. Haskell would force you to spell out the new state as a function of the old state of the system. This would let us do gate-level simulations of the hardware we designed. Coupled with Haskell's penchant for using primes to mean "the new value of", stuff like x' = f x was very common.
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I'm starting a project to make a Rust-like hardware description language and I need your opinions.
You should look at Bluespec, they are doing some interesting stuff.
- Verilog Is Weird
- Bluespec hardware design language and simulation tools
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MyHDL: Using Python as a hardware description and verification language
And I've been involved in a project that's making heavy use of Bluespec: https://github.com/B-Lang-org/bsc/
Same problem though - you have to transpile it down to Verilog to use it in anything beyond a simulation.
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FPGA dev board that's cheap, simple and supported by OSS toolchain
FPGA Thread: Bluespec SystemVerilog is now completely open source, very nice HDL although quite opinionated.
https://github.com/B-Lang-org/bsc
it's Haskell underneath (https://xkcd.com/356/)
ao486_MiSTer
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Reverse engineering the Intel 386 processor's register cell
How about a 486 instead? :)
https://github.com/MiSTer-devel/ao486_MiSTer
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Issues with AO486
Have you checked all the details in https://github.com/MiSTer-devel/ao486_MiSTer ?
- Ao486_MiSTer: i486 core for the MiSTer FPGA gaming system
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Recently, I came across a video on Youtube by Linus Tech Tips about the PCEm emulator that I found to be cringy and ill-informed. As a computer engineer by education let me explain few core concepts on how emulation works.
You mention "Pentium MMX CPU" a few times in your post, but fail to mention any FPGA solution that can emulate a machine of that class. MiSTer can't do that, the best it can do is a 486 (not just missing MMX, doesn't even have an FPU).
- Exact 486 CPU Performance in Smallest Form Factor
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Emulate Any ISA Card With A Raspberry Pi And An FPGA
It has already happened: https://github.com/MiSTer-devel/ao486_MiSTer
- Are there FPGA cores for SB16/ET4KW32/NE2K?
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KEYBCS2
The last processor generation it worked on is the 486, but on a Pentium or newer it always fails with a “Debugging is not allowed” message.
I guessed the reason for that correctly - prefetch queue. Mentions of CUP386 in the comments also brought back more memories of the cracking scene in the late 80s/early 90s. There's some very interesting discussion on SMC vs CPU behaviour here --- in the context of an open-source 486-level SoC core:
https://github.com/MiSTer-devel/ao486_MiSTer/issues/33
What are some alternatives?
chisel - Chisel: A Modern Hardware Design Language
dosbox-x - DOSBox-X fork of the DOSBox project
UPduino-v3.0 - UPduino 3.0: new 4 layer layout, various other improvements
PCem-ROMs - This is a collection of requiered ROMs files for PCem emulator. RIP PCem 2021
PipelineC - A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.
elks - Embeddable Linux Kernel Subset - Linux for 8086
linux-on-litex-vexriscv - Linux on LiteX-VexRiscv
libi86 - Attempt to reimplement non-standard C library facilities (e.g. <conio.h>) used in MS-DOS programs, for IA-16 GCC & ACK ― mirror of https://gitlab.com/tkchia/libi86 • Ubuntu packages for cross-compilation at https://launchpad.net/%7Etkchia/+archive/ubuntu/build-ia16/ • DJGPP/MS-DOS binaries at https://github.com/tkchia/libi86/releases
rustylog - A Rust-like Hardware Description Language transpiled to Verilog
NyuziProcessor - GPGPU microprocessor architecture
fomu-toolchain - A collection of tools for developing for Fomu
vISA