Astro8-Computer
qtrvsim
| Astro8-Computer | qtrvsim | |
|---|---|---|
| 2 | 1 | |
| 665 | 412 | |
| - | 4.1% | |
| 6.2 | 8.9 | |
| about 2 months ago | 4 days ago | |
| C++ | C++ | |
| MIT License | GNU General Public License v3.0 only |
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Astro8-Computer
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Embedded Systems Weekly #112
I Designed My Own 16-bit CPU AstroSam, 16 years old, designed a 16-bit CPU called Astro-8, created an assembly language for it and finally created a compiled language named Armstrong (deal with it). All the video is entertaining and the work is impressive when you take into account Sam's age. All the code and schemas are on GitHub. I also discovered Logisim-evolution tool watching the video.
- I Designed My Own 16-Bit CPU
qtrvsim
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How a CPU works: Bare metal C on my RISC-V toy CPU
- source & native releases: https://github.com/cvut/qtrvsim
It visualizes the inner workings of a basic RISC-V CPU, you can choose a basic single-cycle CPU, or a full 5-stage pipelined CPU with a hazard unit.
I also recently wrote a 5-stage RISC-V CPU in SystemVerilog, the implementation should be reasonably well-commented: https://github.com/MatejKafka/risc-v_pipelined_cpu
What are some alternatives?
cpu_features - A cross platform C99 library to get cpu features at runtime.
Kite - Kite: Architecture Simulator for RISC-V Instruction Set
logisim-evolution - Digital logic design tool and simulator
fpga-experiments
Digital - A digital logic designer and circuit simulator.
cs2410 - An out-of-order execution CPU simulator for CS2410 Computer Architecture course final project at the University of Pittsburgh.
Chimera - Automated DLL Sideloading Tool With EDR Evasion Capabilities
risc-v_pipelined_cpu - RISC-V CPU with a 5-stage pipeline, written in SystemVerilog
Ripes - A graphical processor simulator and assembly editor for the RISC-V ISA