Top 4 Rv32im Open-Source Projects

• riscv

  2 1,040 1.8 Verilog

  RISC-V CPU Core (RV32IM)

Project mention: Ultraembedded RISCV Module | /r/RISCV | 2023-08-04

I have been trying to execute some instructions to the ultraembedded riscv module https://github.com/ultraembedded/riscv

• shecc

  6 1,038 8.7 C

  A self-hosting and educational C optimizing compiler

  

Project mention: A self-hosting and educational C optimizing compiler | news.ycombinator.com | 2024-01-07

Yes, consider the case of shecc. It requires just a handful of C code lines to interpret directives set in the C preprocessor. Unlike relying on existing tools like cpp, as, or ld, shecc stands alone as a minimalist cross-compiler. This design could be particularly beneficial for students delving into the study of compiler construction. See https://github.com/sysprog21/shecc/blob/master/src/lexer.c#L...

• InfluxDB

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• biriscv

  6 749 0.0 Verilog

  32-bit Superscalar RISC-V CPU

Project mention: Need help with designing a basic RISC V processor? | /r/RISCV | 2023-06-21

• kianRiscV

  1 487 7.8 AGS Script

  RISC-V Linux SoC, marchID: 0x2b

Project mention: Have I discovered a synthesis/routing defect with the Gowin IDE? | /r/GowinFPGA | 2023-07-22

I encountered this issue when having difficulty porting a risc-v softcore (https://github.com/splinedrive/kianRiscV/blob/master/README.md), which works perfectly on two other hardware platforms. The linux boot process would stall about 1M instructions in. I tracked the issue down to the above issue, which differed from simulation results. Straightforward attempts to recreate the defect in a standalone environment failed. Instead I have resorted to stripping back and refactoring the failing softcore implementation layer by layer until reaching a minimal setup which still exhibits the defect. The result is the code below. The code doesn’t do anything meaningful, except exhibit the defect.

Rv32im related posts

• Need help with designing a basic RISC V processor?

  5 projects | /r/RISCV | 21 Jun 2023

• Не слабо так у турков бомбануло после сожжения Корана у посольства Турции в Стокгольме

  1 project | /r/tjournal_refugees | 24 Jan 2023

• BiRISC-V – 32-bit Superscalar RISC-V CPU

  1 project | news.ycombinator.com | 20 Jul 2021

• [github] biRISC-V - 32-bit dual issue RISC-V CPU

  1 project | /r/chipdesign | 6 Jan 2021

• [github] biRISC-V - 32-bit dual issue RISC-V CPU

  1 project | /r/RISCV | 6 Jan 2021

• BiRISC-V – 32-bit dual issue RISC-V CPU

  1 project | news.ycombinator.com | 6 Jan 2021
• A note from our sponsor - InfluxDB
  www.influxdata.com | 3 May 2024

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