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Top 12 lattice Open-Source Projects
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InfluxDB
Power Real-Time Data Analytics at Scale. Get real-time insights from all types of time series data with InfluxDB. Ingest, query, and analyze billions of data points in real-time with unbounded cardinality.
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open-fpga-verilog-tutorial
Learn how to design digital systems and synthesize them into an FPGA using only opensource tools
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randar-explanation
"Randar" is an exploit for Minecraft which uses LLL lattice reduction to crack the internal state of an incorrectly reused java.util.Random in the Minecraft server, then works backwards from that to locate other players currently loaded into the world.
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openfhe-development
This is the development repository for the OpenFHE library. The current (stable) version is v1.1.4 (released on March 8, 2024).
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SaaSHub
SaaSHub - Software Alternatives and Reviews. SaaSHub helps you find the best software and product alternatives
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f4pga-arch-defs
FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
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BrianHG-DDR3-Controller
DDR3 Controller v1.60, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow video controller with alpha-blended layers. Docs & TBs included.
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neorv32-setups
📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.
Another way to flash the devices in Linux is to use https://github.com/trabucayre/openFPGALoader which supports a variety of cables and devices. It also supports the Xilinx Virtual Cable protocol, which allows you to use Xilinx tools like ChipScope with almost any cable.
apio is a python package you drive from the command line. I didn't know somebody had done an integration with Atom. I've installed and used apio on my phone. I wouldn't really recommend doing that, but it shows what's possible.
Project mention: How to find the pin mapping for connecting Zybo Z7-20 or Nexyx A7 board to a computer over USB-JTAG? | /r/FPGA | 2023-08-03Hello. In my project, I am trying to run NEORV32 processor in an FPGA. My plan is to perform debugging of the design over JTAG after running it on an FPGA. I currently have a Zybo Z7-20 and a Nexyx A7 board at hand. As per my understanding, for both of the boards, I need to find the board pins associated with JTAG and manually connect them through the constraint file. I was going through the reference manuals for both FPGAs but couldn't find the pins that need to be connected.
lattice related posts
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How to find the pin mapping for connecting Zybo Z7-20 or Nexyx A7 board to a computer over USB-JTAG?
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Looking for help getting started with TinyFPGA
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GAO under Linux
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issue with Gowin 20k and openFPGAloader
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Learning Verilog and FPGA
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[Asking for Help] Tang Nano 9K Programmer - Linux Ubuntu 20.04 - "No USB Cable Connection"
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Icestudio: Drag and Drop FPGA programming and learning
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A note from our sponsor - SaaSHub
www.saashub.com | 6 May 2024
Index
What are some of the best open-source lattice projects? This list will help you:
Project | Stars | |
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1 | icestudio | 1,659 |
2 | openFPGALoader | 1,044 |
3 | apio | 754 |
4 | open-fpga-verilog-tutorial | 743 |
5 | randar-explanation | 609 |
6 | openfhe-development | 604 |
7 | edalize | 593 |
8 | ascent | 370 |
9 | f4pga-arch-defs | 248 |
10 | fpga-docker | 66 |
11 | BrianHG-DDR3-Controller | 60 |
12 | neorv32-setups | 53 |
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