A simple DDR3 memory controller (by promach)

DDR Alternatives

Similar projects and alternatives to DDR

NOTE: The number of mentions on this list indicates mentions on common posts. Hence, a higher number means a better DDR alternative or higher similarity.

Suggest an alternative to DDR


Posts where DDR has been mentioned. We have used some of these posts to build our list of alternatives and similar projects - the last one was on 2021-05-04.
  • Use of IODELAY2 primitive for shifting READ DQS strobe
    reddit.com/r/FPGA | 2021-07-01
    See https://github.com/promach/DDR
  • Xilinx ISE implementation stage issues
    reddit.com/r/FPGA | 2021-06-20
    Could anyone help with the series buffer and multiple drivers issues ?
  • Micron DDR3 memory controller
    reddit.com/r/FPGA | 2021-06-07
    the DDR3 schematics and verilog code are located at https://github.com/promach/DDR
  • FPGA internal logic analyzer
    reddit.com/r/FPGA | 2021-05-04
    ALL the ILA modules that I am having now do not work.
    reddit.com/r/FPGA | 2021-05-04
    but how to source the ILA on the inside of the tri-state buffer ?
    reddit.com/r/FPGA | 2021-05-04
    I am using ISE Chipscope ILA as shown in the picture below. May I know how I actually use CONTROL0 and TRIG0 signals to capture the FPGA signal that I want ? Note: I am trying to debug on this DDR memory controller project at https://github.com/promach/DDR
    reddit.com/r/FPGA | 2021-05-04
    I have already done this. See https://github.com/promach/DDR/blob/main/test_ddr3_memory_controller.v#L88-L96
    reddit.com/r/FPGA | 2021-05-04
    So, how should I connect dq to ILA ?


Basic DDR repo stats
13 days ago

promach/DDR is an open source project licensed under GNU General Public License v3.0 only which is an OSI approved license.