DDR
A simple DDR3 memory controller (by buttercutter)
internal_logic_analyzer
An internal logic analyzer/scope for FPGA's (by buttercutter)
DDR | internal_logic_analyzer | |
---|---|---|
8 | 1 | |
40 | 1 | |
- | - | |
0.0 | 0.0 | |
over 1 year ago | over 6 years ago | |
Verilog | C++ | |
GNU General Public License v3.0 only | GNU General Public License v3.0 only |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
DDR
Posts with mentions or reviews of DDR.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2021-05-04.
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Use of IODELAY2 primitive for shifting READ DQS strobe
See https://github.com/promach/DDR
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Xilinx ISE implementation stage issues
Could anyone help with the series buffer and multiple drivers issues ?
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Micron DDR3 memory controller
the DDR3 schematics and verilog code are located at https://github.com/promach/DDR
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FPGA internal logic analyzer
ALL the ILA modules that I am having now do not work.
internal_logic_analyzer
Posts with mentions or reviews of internal_logic_analyzer.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2021-05-04.
-
FPGA internal logic analyzer
I have written my own ILA module at https://github.com/promach/internal_logic_analyzer . However, I am not sure how to code the verilog module that transmits the data to host cpu as well as the cpu software that actually processes the internally captured FPGA signals/data and display them accordingly ?