FPGA internal logic analyzer

• DDR

  8 40 0.0 Verilog

  A simple DDR3 memory controller

I am using ISE Chipscope ILA as shown in the picture below. May I know how I actually use CONTROL0 and TRIG0 signals to capture the FPGA signal that I want ? Note: I am trying to debug on this DDR memory controller project at https://github.com/promach/DDR

• internal_logic_analyzer

  1 1 0.0 C++

  An internal logic analyzer/scope for FPGA's

I have written my own ILA module at https://github.com/promach/internal_logic_analyzer . However, I am not sure how to code the verilog module that transmits the data to host cpu as well as the cpu software that actually processes the internally captured FPGA signals/data and display them accordingly ?

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