Cwerg Alternatives
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Cwerg reviews and mentions
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Comparing Two Intermediate Languages
Cwerg, which is also three-address based, as a benchmark.
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Update: Extended Basic Blocks, Superblocks, Hyperblocks, Interval Blocks
In Cwerg I do allow function calls in the middle of BBs to increase the average size of a BB a little.
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May 2022 monthly "What are you working on?" thread
The Cwerg compiler backend now has support for simple atomics via a CAS IR instruction. Basic thread support has been added to the StdLib as well (Linux on x86-64, Arm32, Aarch64).
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April 2022 monthly "What are you working on?" thread
a programmatic one where you use the API to construct the Cwerg IR in memory and then let Cwerg produce machine code. An example API usage can be found here: https://github.com/robertmuth/Cwerg/blob/master/Examples/fib_ir.h Here is a context where this is used for JITing but AOT is not much different: https://github.com/robertmuth/Cwerg/blob/master/Examples/jit_ir_x64.cc
For March I had planned to add atomics (really just compare-and-swap aka CAS ) to the Cwerg IR.
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How useful is thread local storage (TLS)
I am debating whether TLS should become a first class citizen in Cwerg so I have been looking into use cases. The size of the TLS segment in a typical (Linux) binary is tiny - tens of bytes - suggesting this feature is not commonly used. The primary use cases I could identify were: * improvements to memory allocation * replication of certain globals (like errno) to make them more thread friendly * integration with Restartable sequences which in turn seem to primarily benefit memory allocation
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Things That Turbo Pascal Is Smaller Than
I have a project going that tries to bring back ultra short compilation times:
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Looking for resources on building a compiler
Shameless plug for the Cwerg compiler backend which consists of
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Cwerg can now emit x86-64 instructions
Cwerg, a new lightweight compiler backend, now targets x86-64 (besides Arm32 and Aarch64).
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Picking atomic instruction primitives for a compiler backend
My compiler backend Cwerg does not yet support atomic instructions. I have looked around a little and the most obvious options are
Sorry, I should have been more clear: The Cwerg IR is a RISC like virtual instructution set. I am trying to enrich it with atomic operations so that inline assembly can be avoided as much as possible. Keeping the size of the IR small is a higher priority than performance of the generated code.
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January 2022 monthly "What are you working on?" thread
I have been working on the x86-64 target for the Cwerg Compiler Backend.
PSA: if you must encode instructions yourself. Save yourself some headache and use pre-existing tables, e.g. asmdb. Cwerg uses them for both encoding and decoding, see: opcode_tab.py.
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Do We Really Need A Link Step?
Cwerg is following this approach. It defines an IR and compiles it all the way to (static) ELF executables. The plan is too make this so fast that for most projects this will become unnoticeable.
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December 2021 monthly "What are you working on?" thread
I finally broke down and started implementing an x86-64 backend for Cwerg.
Stats
robertmuth/Cwerg is an open source project licensed under Apache License 2.0 which is an OSI approved license.
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