Vector-packing algorithm

• hdl_rosetta_stone

  4 4 5.7 Verilog

  writing up a few examples using different languages and tools, mostly for personal learning.

I would write a module that held back the last element in a stream until 8 slots were passed, then let it pass through with a tlast signal. Something like this https://github.com/TripRichert/hdl_rosetta_stone/blob/main/verilog/hdl/axistream_add_tlast.v command the tlast every 8 elements, and don't raise tvalid on your inactive element inputs.

• Experiments

  1 0 4.1 Rust

  Assorted experiments and proof-of-concept code (by ooterness)

I put together a tool to evaluate different sorting networks and came to the same conclusion. There's a few different variants of the bitonic sort, but unfortunately nothing I've tried preserves the original order.

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