Hdl_rosetta_stone Alternatives

Similar projects and alternatives to hdl_rosetta_stone

xpm_vhdl

2 44 3.6 VHDL hdl_rosetta_stone VS xpm_vhdl

A translation of the Xilinx XPM library to VHDL for simulation purposes
Experiments

1 0 4.1 Rust hdl_rosetta_stone VS Experiments

Assorted experiments and proof-of-concept code (by ooterness)
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NOTE: The number of mentions on this list indicates mentions on common posts plus user suggested alternatives. Hence, a higher number means a better hdl_rosetta_stone alternative or higher similarity.

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hdl_rosetta_stone reviews and mentions

Posts with mentions or reviews of hdl_rosetta_stone. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2022-04-25.

Inferred BRAM based FIFO with mismatched input and output data widths
2 projects | /r/FPGA | 25 Apr 2022
Vector-packing algorithm
2 projects | /r/FPGA | 23 Oct 2021

I would write a module that held back the last element in a stream until 8 slots were passed, then let it pass through with a tlast signal. Something like this https://github.com/TripRichert/hdl_rosetta_stone/blob/main/verilog/hdl/axistream_add_tlast.v command the tlast every 8 elements, and don't raise tvalid on your inactive element inputs.
Gearbox FIFO implementation
1 project | /r/FPGA | 17 Oct 2021

https://github.com/TripRichert/hdl_rosetta_stone/blob/main/verilog/hdl/axistream_unpack.v https://github.com/TripRichert/hdl_rosetta_stone/blob/main/verilog/hdl/axistream_unpack.v (where unpack's bitwidth is 2 and NUM_PACK is 32, and pack's bitwidth is 2 and NUM_PACK is 33).
Data flow into a top module
1 project | /r/FPGA | 16 Sep 2021
A note from our sponsor - InfluxDB
www.influxdata.com | 19 Apr 2024

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