Using the GPIO for external inputs and outputs for fancy FPGA projects

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  • FPGAprojects

    Verilog Codes for FPGA projects I did back in 2019, including 5 stage pipelined MIPS CPU.

    • Assuming that you have familiarised yourself with Verilog HDL, the Verilog HDL code I wrote for this exercise would be in my Github.

  • InfluxDB

    Power Real-Time Data Analytics at Scale. Get real-time insights from all types of time series data with InfluxDB. Ingest, query, and analyze billions of data points in real-time with unbounded cardinality.

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