Lutsig - A verified Verilog synthesizer

This page summarizes the projects mentioned and recommended in the original post on reddit.com/r/FPGA

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  • hardware

    Verilog development and verification project for HOL4 (by CakeML)

    All source code and proofs are available on Github: https://github.com/CakeML/hardware. However, if you are not familiar with the HOL4 theorem prover it's not entirely straightforward to run Lutsig since you currently have to run Lutsig inside the theorem prover.

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NOTE: The number of mentions on this list indicates mentions on common posts plus user suggested alternatives. Hence, a higher number means a more popular project.

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