Standard ML Verilog

Open-source Standard ML projects categorized as Verilog Edit details

Standard ML Verilog Projects

  • hardware

    Verilog development and verification project for HOL4 (by CakeML)

    Project mention: There's an ongoing effort to rewrite Principia Mathematica using Coq | reddit.com/r/math | 2021-12-03

    There are ongoing research projects about that, you may want to have a look at Kôika (https://github.com/mit-plv/koika), Kami (https://github.com/mit-plv/kami), Lutsig (https://github.com/CakeML/hardware) and silveroak (https://github.com/project-oak/silveroak). Closer to HLS there is also Vericert (https://github.com/ymherklotz/vericert). There may be other research project I am unaware of, feel free to add them in a reply, I am interested in it.

  • talent.io

    Download talent.io’s Tech Salary Report. Median salaries, most in-demand technologies, state of the remote work... all you need to know your worth on the market by tech recruitment platform talent.io

NOTE: The open source projects on this list are ordered by number of github stars. The number of mentions indicates repo mentiontions in the last 12 Months or since we started tracking (Dec 2020). The latest post mention was on 2021-12-03.

Standard ML Verilog related posts

Index

Project Stars
1 hardware 15
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