Standard ML Verilog Projects
Verilog development and verification project for HOL4 (by CakeML)Project mention: There's an ongoing effort to rewrite Principia Mathematica using Coq | reddit.com/r/math | 2021-12-03
There are ongoing research projects about that, you may want to have a look at Kôika (https://github.com/mit-plv/koika), Kami (https://github.com/mit-plv/kami), Lutsig (https://github.com/CakeML/hardware) and silveroak (https://github.com/project-oak/silveroak). Closer to HLS there is also Vericert (https://github.com/ymherklotz/vericert). There may be other research project I am unaware of, feel free to add them in a reply, I am interested in it.
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