Standard ML Verilog

Open-source Standard ML projects categorized as Verilog

Standard ML Verilog Projects

  • hardware

    Verilog development and verification project for HOL4 (by CakeML)

  • InfluxDB

    Power Real-Time Data Analytics at Scale. Get real-time insights from all types of time series data with InfluxDB. Ingest, query, and analyze billions of data points in real-time with unbounded cardinality.

    InfluxDB logo
NOTE: The open source projects on this list are ordered by number of github stars. The number of mentions indicates repo mentiontions in the last 12 Months or since we started tracking (Dec 2020).

Standard ML Verilog related posts

  • Lutsig - A verified Verilog synthesizer

    1 project | /r/FPGA | 11 Jan 2021


Project Stars
1 hardware 22

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