CPU Design Verification Interview

• uvmprimer

  2 427 0.0 SystemVerilog

  Contains the code examples from The UVM Primer Book sorted by chapters.

If you don't know UVM you are not at a disadvantage; you can learn on the job looking at existing code, learn the company testbench design, etc. Even in interviews many of the UVM questions are not in-depth ones asking to write full-on testbench components, rather small ones like "how do you connect a scoreboard to a monitor" where you'd need to know on a surface level about analysis ports, TLM FIFOs, the write() function to dump data into ports, and how to connect ports from one component to another. I'd heavily suggest reading The UVM Primer by Ray Salemi you'll find PDFs online, and looking in parallel at the same examples from the book on the github repo. Spend like a week or two reading the book and it's contents and you'll be very set for typical UVM questions that may come up.

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