How hard would it be to write fractional 0-1 informational states in different media off the shelf (RAM, HDD, SSD, etc? And w/ controller hacks allowed?)

• sigma_delta_converters

  1 31 10.0 SystemVerilog

  Implementation and test of reusable sigma-delta A/D converters written in SystemVerilog on a MAX10 FPGA with minimal external components

Also: https://github.com/davemuscle/sigma_delta_converters if you are stuck with a more generic FPGA and want to implement ADC/DAC (as much as you can) inside a FPGA.

• InfluxDB

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