Sipeed Tang Nano 4K, 9K (Gowin FPGAs) become unstable when lots of flip flops are in use

• gowin_flipflop_drainer

  8 21 1.1 Verilog

  A test case for stress testing Tang Nano 4K and 9K and Primer 20K (Gowin FPGAs)

You can find the test case repository at https://github.com/juj/gowin_flipflop_drainer

• tang4Kramblings

  1 19 10.0 GLSL

I'm relatively new to FPGAs myself, but I thought about this project. He claims to be using 70% of the logic resources of a Nano 4K and achieves 720p@60Hz. Have you tried to run this design and see if you experience the same problems?

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