vhdl-tutorial
prince
| vhdl-tutorial | prince | |
|---|---|---|
| 1 | 1 | |
| 67 | 7 | |
| - | - | |
| 4.0 | 3.5 | |
| 9 months ago | 4 months ago | |
| VHDL | Verilog | |
| GNU General Public License v3.0 only | BSD 2-clause "Simplified" License |
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vhdl-tutorial
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Learning Verilog and FPGA
Greg Stitt shares amazing training materials freely (he uses them for his undergraduate and graduate courses). His synthesizable HDL methods are really empowering for beginner developers
https://github.com/ARC-Lab-UF/vhdl-tutorial
http://www.gstitt.ece.ufl.edu/
prince
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Learning Verilog and FPGA
I would also recommend to use non-blocking assignments only for register updates, not in any description of combinational logic. It is (IMHO) much easier to read Verilog code with blocking assignments for logic since you basically can read the statements one after the other and mentally think that the RHS on a statement has been updated.
IF I may point to my own code, the prince cipher core shows how I use non-blocking assignments in a very simple reg update process. The datapath is in a separate, pure combinational process. And the control path is handled by the finite state machine update logic process at the end.
https://github.com/secworks/prince/blob/master/src/rtl/princ...
The SystemVerilog always_comb and always_ff type of processes makes the distincion much clearer. But the same strategy holds for Verilog, and IMHO helps out understand the code. And often makes it less complex.
What are some alternatives?
apio - :seedling: Open source ecosystem for open FPGA boards
icestorm - Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentation (Reverse Engineered)
prjtrellis - Documenting the Lattice ECP5 bit-stream format.
6502-exp - 6502 Computer FPGA Peripherals
f4pga-arch-defs - FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.