veryl
Veryl: A Modern Hardware Description Language (by veryl-lang)
svls
SystemVerilog language server (by dalance)
| veryl | svls | |
|---|---|---|
| 8 | 3 | |
| 490 | 457 | |
| 4.1% | - | |
| 9.8 | 8.2 | |
| 3 days ago | 13 days ago | |
| Rust | Rust | |
| GNU General Public License v3.0 or later | MIT License |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
veryl
Posts with mentions or reviews of veryl.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2024-03-12.
- Veryl v0.12.0: A New Hardware Description Language
- Veryl: A Modern Hardware Description Language
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How to keep files in memory in tower_lsp?
The another solution is that spliting mutable struct to another thread, and communicating through async_channel. See the following changes. https://github.com/dalance/veryl/pull/155
- Veryl v0.4.0 release
- Veryl: A modern hardware description language
svls
Posts with mentions or reviews of svls.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2023-06-27.
-
How to configure vim like an IDE
svls
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Julia Receives DARPA Award to Accelerate Electronics Simulation by 1,000x
I can attest first-hand to the "headache" that comes from semi company simulation environments. Not only are they horribly outdated (in Perl/Tcl), but they're different at every company you work at. There's no gold standard because the standard that these EDA companies ought to be making doesn't exist.
There needs to be an open initiative between semi companies to create a standard simulation environment -- with compilers, unit-test frameworks, and all sorts of simulation (gate-level, analog/mixed signal, emulation, etc). Hell, just give me a free IDE plugin for SystemVerilog that actually works.
This lack of a standard seems to me like the critical path in hardware design. I'm trying to support projects to fix this like SVLS (A language server for SystemVerilog: https://github.com/dalance/svls) but these are all hard problems to solve. This industry is relatively niche and doesn't seem to have many engineers interested in FOSS.