veryl
Veryl: A Modern Hardware Description Language (by veryl-lang)
rggen
Code generation tool for control and status registers (by rggen)
| veryl | rggen | |
|---|---|---|
| 8 | 3 | |
| 479 | 319 | |
| 1.9% | 0.9% | |
| 9.8 | 7.0 | |
| 4 days ago | 3 months ago | |
| Rust | Ruby | |
| GNU General Public License v3.0 or later | MIT License |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
veryl
Posts with mentions or reviews of veryl.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2024-03-12.
- Veryl v0.12.0: A New Hardware Description Language
- Veryl: A Modern Hardware Description Language
-
How to keep files in memory in tower_lsp?
The another solution is that spliting mutable struct to another thread, and communicating through async_channel. See the following changes. https://github.com/dalance/veryl/pull/155
- Veryl v0.4.0 release
- Veryl: A modern hardware description language
rggen
Posts with mentions or reviews of rggen.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2022-06-13.
-
RgGen v0.28.0
I've released RgGen v0.28.0! https://github.com/rggen/rggen/releases/tag/v0.28.0 This release includes following updates.
-
RgGen update (support C header file generation)
RgGen is a code generation tool for configuration and status registers. RgGen can generate SV/Verilog/VHDL RTL, UVM RAL model and Markdown documents from readable register map specifications. https://github.com/rggen/rggen
-
RgGen update
I just released the latest RgGen v0.26.0! https://github.com/rggen/rggen/releases/tag/v0.26.0
What are some alternatives?
When comparing veryl and rggen you can also consider the following projects:
svlint - SystemVerilog linter
PeakRDL-uvm - Generate UVM register model from compiled SystemRDL input