verilog-wishbone
Verilog wishbone components (by alexforencich)
fiate
Fault Injection Automatic Test Equipment (by byuccl)
Our great sponsors
| verilog-wishbone | fiate | |
|---|---|---|
| 1 | 4 | |
| 98 | 7 | |
| - | - | |
| 0.0 | 0.0 | |
| 4 months ago | over 2 years ago | |
| Python | VHDL | |
| MIT License | Apache License 2.0 |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
verilog-wishbone
Posts with mentions or reviews of verilog-wishbone.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2021-09-14.
-
Share some github FPGA projects (bonus if they include C++, Python, or other files)
A lot of reuse from other FOSH projects, including Litex, SpinalHDL, betrusted & u/alexforencich verilog-wishbone. Thanks to all of them :-)
fiate
Posts with mentions or reviews of fiate.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2021-09-14.
-
Building xvc_pup device drivers from the source.
Try this: https://github.com/byuccl/fiate/blob/main/host_sw/xvc.py There are other GitHub examples as well. https://github.com/search?q=xilinx+virtual+cable
-
Help setting up Xilinx Artix-7 FPGA (RHS Labs Litefury FPGA board)
Here is my Github work with the SQRL Acorn (same design as the litefury): https://github.com/byuccl/fiate
-
SPI flash command set specification
I have that part in a few SQRL acorn FPGAs. Here is my python wrapper for the Xilinx QSPI device. https://github.com/byuccl/fiate/blob/main/host_sw/qspi.py
- Share some github FPGA projects (bonus if they include C++, Python, or other files)
What are some alternatives?
When comparing verilog-wishbone and fiate you can also consider the following projects:
litex - Build your hardware, easily!
verilog-ethernet - Verilog Ethernet components for FPGA implementation
SpinalHDL - Scala based HDL
soft_riscv - Soft-core RISCV processor for RISCV 2018 competition
WARP_Core - Wilson AXI RISCV Processor Core
satcat5 - SatCat5 is a mixed-media Ethernet switch that lets a variety of devices communicate on the same network.
BYU_PYNQ_PR_Video_Pipeline - The Demo that was presented at FCCM.
SBusFPGA - Stuff to put a FPGA in a SBus system (SPARCstation)
corundum - Open source FPGA-based NIC and platform for in-network compute
verilog-wishbone vs litex
fiate vs verilog-ethernet
verilog-wishbone vs verilog-ethernet
fiate vs SpinalHDL
verilog-wishbone vs soft_riscv
fiate vs WARP_Core
verilog-wishbone vs SpinalHDL
fiate vs satcat5
verilog-wishbone vs BYU_PYNQ_PR_Video_Pipeline
fiate vs SBusFPGA
verilog-wishbone vs corundum
fiate vs litex