advent-of-code-2022 VS riscv-bitmanip

Compare advent-of-code-2022 vs riscv-bitmanip and see what are their differences.

advent-of-code-2022

πŸŽ„ My Advent of Code solutions in Rust. http://adventofcode.com/2022 (by timvisee)

riscv-bitmanip

Working draft of the proposed RISC-V Bitmanipulation extension (by riscv)
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advent-of-code-2022 riscv-bitmanip
7 12
161 206
- 2.9%
3.6 0.0
5 months ago about 1 month ago
Rust Makefile
GNU General Public License v3.0 only Creative Commons Attribution 4.0
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.

advent-of-code-2022

Posts with mentions or reviews of advent-of-code-2022. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2023-04-24.

riscv-bitmanip

Posts with mentions or reviews of riscv-bitmanip. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2023-08-13.
  • You Won’t Believe This One Weird CPU Instruction (2019)
    2 projects | news.ycombinator.com | 13 Aug 2023
    The bit manipulation [0] extension has been ratified for a while now and is part of the RVA22 application extension profile [1].

    You can already buy SOCs that support it, e.g. vision five 2 and star64.

    Interestingly the risc-v vector has it's own popcount instructions for vector registers/register masks. This is needed, because the scalable architecture doesn't guarantee that a vector mask can fit into a 64 bit register, so vector masks are stored in a single LMUL=1 register. This works really well, because with LMUL=8 and SEW=8 you get 100% utilization of the single LMUL=1 vector register.

    Another interesting thing is that the vector crypto extension will likely introduce a element wise popcount instruction.

    [0] https://github.com/riscv/riscv-bitmanip/releases/download/1....

    [1] https://github.com/riscv/riscv-profiles/blob/main/profiles.a...

  • Is Bit Manipulation extension ratified?
    1 project | /r/RISCV | 2 Jun 2023
    According to latest version of spec on GitHub (https://github.com/riscv/riscv-bitmanip) Bit-manip is in frozen state. Is this ratified and not updated in the sepc document or is it actually frozen?
  • Hand optimised RISC-V assembly language clz
    1 project | /r/RISCV | 29 Apr 2023
  • Testing for presence of _Zba and _Zbb
    2 projects | /r/RISCV | 2 Mar 2023
    I guess 0x20a52533 is a specific _zba instruction? Which one? I searched for "001000" (the left 6 bits of 0x20) in https://github.com/riscv/riscv-bitmanip/releases/download/1.0.0/bitmanip-1.0.0-38-g865e7a7.pdf , but couldn't find a match? Might be PEBKAC.
  • A Neat XOR Trick
    6 projects | news.ycombinator.com | 13 Dec 2022
    RISC-V does have a proposed extension Zbb that includes the cpop and cpopw instructions. It doesn't seem to have much recent activity, though.

    https://github.com/riscv/riscv-bitmanip/blob/main/bitmanip/i...

  • Why aren't there any RISC-V cores with desktop level power?
    1 project | /r/RISCV | 29 Aug 2022
  • Cores with V-extension and Linux support
    1 project | /r/RISCV | 28 Aug 2022
    Enabling B use in dynamically linked libc code will improve every application, especially for example use of orc.b in the C string functions, which is what I invented it for https://github.com/riscv/riscv-bitmanip/issues/41 (using V is even better, but that's optional in RVA22)
  • Bitmanip: Missing bit field extract / insert instructions?
    1 project | /r/RISCV | 3 Jan 2022
    [2] https://github.com/riscv/riscv-bitmanip/releases/tag/1.0.0
  • gmp: "Risc V is a terrible architecture"
    1 project | /r/programming | 7 Dec 2021
    There was a pick instruction, literally named cmov, in an older version of the B (bitmanip) extension (all the good stuff is in extensions). But it seems like it got canned or something, it's not in it anymore (various other interesting instructions were also lost). Silly if you ask me, but I haven't kept up with any of the debate, maybe there's a decent reason..
  • RISC-V Int. Ratifies 15 New Specs, Opening Up New RISC-V Design Possibilities
    6 projects | news.ycombinator.com | 2 Dec 2021
    Yoe maybe interested in the just ratified "RISC-V Bit-Manipulation ISA-extensions" https://github.com/riscv/riscv-bitmanip/releases/download/1....

What are some alternatives?

When comparing advent-of-code-2022 and riscv-bitmanip you can also consider the following projects:

advent - Solutions to https://adventofcode.com/

riscv-v-spec - Working draft of the proposed RISC-V V vector extension

advent-of-code

riscv-sbi-doc - Documentation for the RISC-V Supervisor Binary Interface

adventofcode - My solutions to the Advent of Code challenges

riscv-isa-manual - RISC-V Instruction Set Manual

Advent-of-Code - A collection of my solutions for "Advent of Code"

riscv-crypto - RISC-V cryptography extensions standardisation work.

advent-of-code - My solutions to the Advent of Code

nytm-spelling-bee - Generate anagram puzzles like Frank Longo's "Spelling Bee" as in New York Times Magazine

aoc2022 - Advent of Code 2022 on SCAMP

cpu_features - A cross platform C99 library to get cpu features at runtime.