advent-of-code-2022
riscv-bitmanip
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advent-of-code-2022 | riscv-bitmanip | |
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7 | 12 | |
161 | 206 | |
- | 2.9% | |
3.6 | 0.0 | |
5 months ago | about 1 month ago | |
Rust | Makefile | |
GNU General Public License v3.0 only | Creative Commons Attribution 4.0 |
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advent-of-code-2022
- What is the best way to learn Rust for offensive cybersecurity?
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58 Rust Resources Every Learner Should Know in 2023
18. π¨π΄ Advent of Code is a yearly event where you can solve small (but high-quality) programming puzzles in any language you want. It can be applied to any language that you are learning. You might find this, this, and this repo useful as well where they provide templates and solutions for prior years.
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Hey Rustaceans! Got a question? Ask here (3/2023)!
Is there a conventional meaning for a function named sh? This guy uses it in Q7 of AoC2022, and I wonder why?
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A Neat XOR Trick
I did something similar and counted from the end, to make much bigger jumps!
https://github.com/timvisee/advent-of-code-2022/blob/master/...
Maybe a bit less neat in the binary sense, but definitely very fast.
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-π- 2022 Day 11 Solutions -π-
Part 2 5.72 ms
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-π- 2022 Day 8 Solutions -π-
I'm using the guy who does "the entire AoC in less than a sceond"'s timing code, so I assume it's kosher
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-π- 2022 Day 1 Solutions -π-
Part 1 0.027ms (27 ΞΌs)
riscv-bitmanip
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You Wonβt Believe This One Weird CPU Instruction (2019)
The bit manipulation [0] extension has been ratified for a while now and is part of the RVA22 application extension profile [1].
You can already buy SOCs that support it, e.g. vision five 2 and star64.
Interestingly the risc-v vector has it's own popcount instructions for vector registers/register masks. This is needed, because the scalable architecture doesn't guarantee that a vector mask can fit into a 64 bit register, so vector masks are stored in a single LMUL=1 register. This works really well, because with LMUL=8 and SEW=8 you get 100% utilization of the single LMUL=1 vector register.
Another interesting thing is that the vector crypto extension will likely introduce a element wise popcount instruction.
[0] https://github.com/riscv/riscv-bitmanip/releases/download/1....
[1] https://github.com/riscv/riscv-profiles/blob/main/profiles.a...
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Is Bit Manipulation extension ratified?
According to latest version of spec on GitHub (https://github.com/riscv/riscv-bitmanip) Bit-manip is in frozen state. Is this ratified and not updated in the sepc document or is it actually frozen?
- Hand optimised RISC-V assembly language clz
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Testing for presence of _Zba and _Zbb
I guess 0x20a52533 is a specific _zba instruction? Which one? I searched for "001000" (the left 6 bits of 0x20) in https://github.com/riscv/riscv-bitmanip/releases/download/1.0.0/bitmanip-1.0.0-38-g865e7a7.pdf , but couldn't find a match? Might be PEBKAC.
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A Neat XOR Trick
RISC-V does have a proposed extension Zbb that includes the cpop and cpopw instructions. It doesn't seem to have much recent activity, though.
https://github.com/riscv/riscv-bitmanip/blob/main/bitmanip/i...
- Why aren't there any RISC-V cores with desktop level power?
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Cores with V-extension and Linux support
Enabling B use in dynamically linked libc code will improve every application, especially for example use of orc.b in the C string functions, which is what I invented it for https://github.com/riscv/riscv-bitmanip/issues/41 (using V is even better, but that's optional in RVA22)
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Bitmanip: Missing bit field extract / insert instructions?
[2] https://github.com/riscv/riscv-bitmanip/releases/tag/1.0.0
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gmp: "Risc V is a terrible architecture"
There was a pick instruction, literally named cmov, in an older version of the B (bitmanip) extension (all the good stuff is in extensions). But it seems like it got canned or something, it's not in it anymore (various other interesting instructions were also lost). Silly if you ask me, but I haven't kept up with any of the debate, maybe there's a decent reason..
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RISC-V Int. Ratifies 15 New Specs, Opening Up New RISC-V Design Possibilities
Yoe maybe interested in the just ratified "RISC-V Bit-Manipulation ISA-extensions" https://github.com/riscv/riscv-bitmanip/releases/download/1....
What are some alternatives?
advent - Solutions to https://adventofcode.com/
riscv-v-spec - Working draft of the proposed RISC-V V vector extension
advent-of-code
riscv-sbi-doc - Documentation for the RISC-V Supervisor Binary Interface
adventofcode - My solutions to the Advent of Code challenges
riscv-isa-manual - RISC-V Instruction Set Manual
Advent-of-Code - A collection of my solutions for "Advent of Code"
riscv-crypto - RISC-V cryptography extensions standardisation work.
advent-of-code - My solutions to the Advent of Code
nytm-spelling-bee - Generate anagram puzzles like Frank Longo's "Spelling Bee" as in New York Times Magazine
aoc2022 - Advent of Code 2022 on SCAMP
cpu_features - A cross platform C99 library to get cpu features at runtime.