riscv-bitmanip
riscv-crypto
riscv-bitmanip | riscv-crypto | |
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12 | 8 | |
206 | 345 | |
2.9% | 0.6% | |
0.0 | 7.3 | |
about 2 months ago | 2 months ago | |
Makefile | C | |
Creative Commons Attribution 4.0 | Creative Commons Attribution 4.0 |
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riscv-bitmanip
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You Won’t Believe This One Weird CPU Instruction (2019)
The bit manipulation [0] extension has been ratified for a while now and is part of the RVA22 application extension profile [1].
You can already buy SOCs that support it, e.g. vision five 2 and star64.
Interestingly the risc-v vector has it's own popcount instructions for vector registers/register masks. This is needed, because the scalable architecture doesn't guarantee that a vector mask can fit into a 64 bit register, so vector masks are stored in a single LMUL=1 register. This works really well, because with LMUL=8 and SEW=8 you get 100% utilization of the single LMUL=1 vector register.
Another interesting thing is that the vector crypto extension will likely introduce a element wise popcount instruction.
[0] https://github.com/riscv/riscv-bitmanip/releases/download/1....
[1] https://github.com/riscv/riscv-profiles/blob/main/profiles.a...
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Is Bit Manipulation extension ratified?
According to latest version of spec on GitHub (https://github.com/riscv/riscv-bitmanip) Bit-manip is in frozen state. Is this ratified and not updated in the sepc document or is it actually frozen?
- Hand optimised RISC-V assembly language clz
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Testing for presence of _Zba and _Zbb
I guess 0x20a52533 is a specific _zba instruction? Which one? I searched for "001000" (the left 6 bits of 0x20) in https://github.com/riscv/riscv-bitmanip/releases/download/1.0.0/bitmanip-1.0.0-38-g865e7a7.pdf , but couldn't find a match? Might be PEBKAC.
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A Neat XOR Trick
RISC-V does have a proposed extension Zbb that includes the cpop and cpopw instructions. It doesn't seem to have much recent activity, though.
https://github.com/riscv/riscv-bitmanip/blob/main/bitmanip/i...
- Why aren't there any RISC-V cores with desktop level power?
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Cores with V-extension and Linux support
Enabling B use in dynamically linked libc code will improve every application, especially for example use of orc.b in the C string functions, which is what I invented it for https://github.com/riscv/riscv-bitmanip/issues/41 (using V is even better, but that's optional in RVA22)
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Bitmanip: Missing bit field extract / insert instructions?
[2] https://github.com/riscv/riscv-bitmanip/releases/tag/1.0.0
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gmp: "Risc V is a terrible architecture"
There was a pick instruction, literally named cmov, in an older version of the B (bitmanip) extension (all the good stuff is in extensions). But it seems like it got canned or something, it's not in it anymore (various other interesting instructions were also lost). Silly if you ask me, but I haven't kept up with any of the debate, maybe there's a decent reason..
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RISC-V Int. Ratifies 15 New Specs, Opening Up New RISC-V Design Possibilities
Yoe maybe interested in the just ratified "RISC-V Bit-Manipulation ISA-extensions" https://github.com/riscv/riscv-bitmanip/releases/download/1....
riscv-crypto
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Vector vs SIMD
...and given time, they will likely get the necessary facilities and extensions to compete with packed SIMD in every field (e.g. the cryptography extension makes use of vector element groups in order to operate on 128 bits at a time - which is not possible in a "pure" vector ISA with 32/64-bit vector elements).
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RISC-V announces ratification of it's new Scalar Cryptography & Entropy Source Extensions
Link to the spec: https://github.com/riscv/riscv-crypto/releases
- RISC-V Int. Ratifies 15 New Specs, Opening Up New RISC-V Design Possibilities
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Suggestions for Capstone Projects/Thesis Topics for Post-Graduation Studies in the domain of RISC-V's Security Aspects
What would be the impact of Cryptographic Extension of the RISC-V ISA be, particularly on small IoT devices?
- r/crypto - The RISC-V Scalar Cryptography Extension has reached public review
- The RISC-V Scalar Cryptography Extension has reached public review
- RISC-V Scalar Cryptography Extension reaches public review
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Scalar Cryptography Extensions out for Public Review
Direct link to the latest specification release: https://github.com/riscv/riscv-crypto/releases
What are some alternatives?
riscv-v-spec - Working draft of the proposed RISC-V V vector extension
riscv-sbi-doc - Documentation for the RISC-V Supervisor Binary Interface
riscv-isa-manual - RISC-V Instruction Set Manual
riscv-platform-specs - RISC-V Profiles and Platform Specification
nytm-spelling-bee - Generate anagram puzzles like Frank Longo's "Spelling Bee" as in New York Times Magazine
cpu_features - A cross platform C99 library to get cpu features at runtime.
adventofcode2022_day06
riscv-profiles - RISC-V Architecture Profiles
advent-of-code-2022 - 🎄 My Advent of Code solutions in Rust. http://adventofcode.com/2022