Riscv-bitmanip Alternatives

Similar projects and alternatives to riscv-bitmanip

riscv-v-spec

43 858 6.0 Assembly riscv-bitmanip VS riscv-v-spec

Discontinued Working draft of the proposed RISC-V V vector extension
riscv-isa-manual

41 3,282 9.7 TeX riscv-bitmanip VS riscv-isa-manual

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riscv-profiles

21 87 8.0 Makefile riscv-bitmanip VS riscv-profiles

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advent

17 5 6.5 Go riscv-bitmanip VS advent

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riscv-crypto

8 344 7.3 C riscv-bitmanip VS riscv-crypto

RISC-V cryptography extensions standardisation work.
riscv-sbi-doc

5 316 7.5 Makefile riscv-bitmanip VS riscv-sbi-doc

Documentation for the RISC-V Supervisor Binary Interface
riscv-platform-specs

9 109 0.0 Makefile riscv-bitmanip VS riscv-platform-specs

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advent-of-code-2022

7 161 3.6 Rust riscv-bitmanip VS advent-of-code-2022

🎄 My Advent of Code solutions in Rust. http://adventofcode.com/2022 (by timvisee)
nytm-spelling-bee

2 32 0.0 C++ riscv-bitmanip VS nytm-spelling-bee

Generate anagram puzzles like Frank Longo's "Spelling Bee" as in New York Times Magazine
cpu_features

2 2,374 6.8 C++ riscv-bitmanip VS cpu_features

A cross platform C99 library to get cpu features at runtime.
jdk8u-jdk

6 158 10.0 Java riscv-bitmanip VS jdk8u-jdk
adventofcode2022_day06

1 0 10.0 Rust riscv-bitmanip VS adventofcode2022_day06
advent-of-code-2022

1 3 10.0 riscv-bitmanip VS advent-of-code-2022

NOTE: The number of mentions on this list indicates mentions on common posts plus user suggested alternatives. Hence, a higher number means a better riscv-bitmanip alternative or higher similarity.

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riscv-bitmanip reviews and mentions

Posts with mentions or reviews of riscv-bitmanip. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2023-08-13.

You Won’t Believe This One Weird CPU Instruction (2019)
2 projects | news.ycombinator.com | 13 Aug 2023

The bit manipulation [0] extension has been ratified for a while now and is part of the RVA22 application extension profile [1].
You can already buy SOCs that support it, e.g. vision five 2 and star64.
Interestingly the risc-v vector has it's own popcount instructions for vector registers/register masks. This is needed, because the scalable architecture doesn't guarantee that a vector mask can fit into a 64 bit register, so vector masks are stored in a single LMUL=1 register. This works really well, because with LMUL=8 and SEW=8 you get 100% utilization of the single LMUL=1 vector register.
Another interesting thing is that the vector crypto extension will likely introduce a element wise popcount instruction.
[0] https://github.com/riscv/riscv-bitmanip/releases/download/1....
[1] https://github.com/riscv/riscv-profiles/blob/main/profiles.a...
Is Bit Manipulation extension ratified?
1 project | /r/RISCV | 2 Jun 2023

According to latest version of spec on GitHub (https://github.com/riscv/riscv-bitmanip) Bit-manip is in frozen state. Is this ratified and not updated in the sepc document or is it actually frozen?
Hand optimised RISC-V assembly language clz
1 project | /r/RISCV | 29 Apr 2023
Testing for presence of _Zba and _Zbb
2 projects | /r/RISCV | 2 Mar 2023

I guess 0x20a52533 is a specific _zba instruction? Which one? I searched for "001000" (the left 6 bits of 0x20) in https://github.com/riscv/riscv-bitmanip/releases/download/1.0.0/bitmanip-1.0.0-38-g865e7a7.pdf , but couldn't find a match? Might be PEBKAC.
A Neat XOR Trick
6 projects | news.ycombinator.com | 13 Dec 2022

RISC-V does have a proposed extension Zbb that includes the cpop and cpopw instructions. It doesn't seem to have much recent activity, though.
https://github.com/riscv/riscv-bitmanip/blob/main/bitmanip/i...
Why aren't there any RISC-V cores with desktop level power?
1 project | /r/RISCV | 29 Aug 2022
Cores with V-extension and Linux support
1 project | /r/RISCV | 28 Aug 2022

Enabling B use in dynamically linked libc code will improve every application, especially for example use of orc.b in the C string functions, which is what I invented it for https://github.com/riscv/riscv-bitmanip/issues/41 (using V is even better, but that's optional in RVA22)
Bitmanip: Missing bit field extract / insert instructions?
1 project | /r/RISCV | 3 Jan 2022

[2] https://github.com/riscv/riscv-bitmanip/releases/tag/1.0.0
gmp: "Risc V is a terrible architecture"
1 project | /r/programming | 7 Dec 2021

There was a pick instruction, literally named cmov, in an older version of the B (bitmanip) extension (all the good stuff is in extensions). But it seems like it got canned or something, it's not in it anymore (various other interesting instructions were also lost). Silly if you ask me, but I haven't kept up with any of the debate, maybe there's a decent reason..
RISC-V Int. Ratifies 15 New Specs, Opening Up New RISC-V Design Possibilities
6 projects | news.ycombinator.com | 2 Dec 2021

Yoe maybe interested in the just ratified "RISC-V Bit-Manipulation ISA-extensions" https://github.com/riscv/riscv-bitmanip/releases/download/1....
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