skillbridge
systemrdl-compiler
| skillbridge | systemrdl-compiler | |
|---|---|---|
| 1 | 1 | |
| 160 | 222 | |
| 1.9% | 0.9% | |
| 8.1 | 7.3 | |
| 13 days ago | about 1 month ago | |
| Python | Python | |
| GNU Lesser General Public License v3.0 only | MIT License |
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skillbridge
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Does Synopsis or Cadence tools make your job easier or harder? Asking for back end design, but I'd like to hear from front end as well.
I have had great experiences using this tool here: https://github.com/unihd-cag/skillbridge
systemrdl-compiler
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Tool to generate table of memory-mapped register?
Also I would recommend SystemRDL for creating a definition usable in code generators: https://github.com/SystemRDL/systemrdl-compiler
What are some alternatives?
cadence-python - Python framework for Cadence Workflow Service
PeakRDL-halcpp - C++ 17 Hardware abstraction layer generator from systemrdl
skywater-pdk - Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.
PeakRDL-ipxact - Import and export IP-XACT XML register models
pygears - HW Design: A Functional Approach
PeakRDL-html - Generate address space documentation HTML from compiled SystemRDL input
scapy - Scapy: the Python-based interactive packet manipulation program & library.
wavedrom - :ocean: Digital timing diagram rendering engine
rggen - Code generation tool for control and status registers
joes-sandbox
mrisc32 - MRSIC32 ISA documentation and development
PeakRDL-pdf - Converts the SystemRDL data into pdf Register specification