riscv_verilator_model
RISCV model for Verilator/FPGA targets (by aignacio)
gdb-stub
gdb-proxy implementation for bonfire (by bonfireprocessor)
| riscv_verilator_model | gdb-stub | |
|---|---|---|
| 2 | 1 | |
| 40 | 0 | |
| - | - | |
| 0.0 | 3.7 | |
| over 4 years ago | 10 months ago | |
| C | C | |
| Apache License 2.0 | MIT License |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
riscv_verilator_model
Posts with mentions or reviews of riscv_verilator_model.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2021-08-29.
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RISCV sim through Verilator
So far I have found only this repo : https://github.com/aignacio/riscv_verilator_model.git (does not work for me yet)
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Need help in CPU design
https://github.com/aignacio/riscv_verilator_model Good start...
gdb-stub
Posts with mentions or reviews of gdb-stub.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2021-03-22.
-
Need help in CPU design
Regarding debug, very few open source cores support anything approaching the kind of debug interface you would find on a microcontroller or vendor core (breakpoints, single stepping and memory viewers). Supporting these features involves considerable extra hardware and some special software to interface with GDB, called a GDB stub. The Bonfire CPU has support for a GDB stub but I've never tried it.
What are some alternatives?
When comparing riscv_verilator_model and gdb-stub you can also consider the following projects:
serv - SERV - The SErial RISC-V CPU
riscv-simple-sv - A simple RISC V core for teaching
neorv32 - :rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
picoMIPS - picoMIPS processor doing affine transformation