riscv-ocelot
ara
| riscv-ocelot | ara | |
|---|---|---|
| 5 | 5 | |
| 135 | 307 | |
| 2.2% | 2.9% | |
| 9.2 | 7.5 | |
| 6 months ago | about 1 month ago | |
| Scala | C | |
| BSD 3-clause "New" or "Revised" License | GNU General Public License v3.0 or later |
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For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
riscv-ocelot
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Final Year Project on RISC-V?
If it helps you determine estimates etc. there is the https://github.com/tenstorrent/riscv-ocelot project, "Ocelot: The Berkeley Out-of-Order RISC-V Processor with Vector Support". And that has RVV 1.0 support apparently.
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Open-source high-performance RISC-V processor
Some people might be interested in Ocelot:
https://github.com/tenstorrent/riscv-ocelot
Its basically the evolved BOOM Core from Berkley but with a full RISC-V Vector Unit attached.
I had really hoped more people put more investment in BOOM.
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How good is tensetorrent ?
So far it's hard to understand now. Of interest is their open source project ocelot - vpu based on risc-v vector spec https://github.com/tenstorrent/riscv-ocelot
- I’m not expert, but I guess it is worth to check out
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Tenstorrent releases open source 512 VLEN vector unit integrated with BOOM RISC-V core
GitHub: https://github.com/tenstorrent/riscv-ocelot
ara
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x86 vs ARM; Vector and Matrix Extensions; How do they compare?
yeah, ara also currently doesn't work, but that it exist is already really cool, and will likely get fixed and completed in the future
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Ara2: RVV 1.0 Compliant Open-Source Processor
The ISA is variable length/scalable, but this implementation uses a 4096 wide register file.
They are a bit disingenuous in claiming they support rvv 1.0 while others only a subset, as they haven't implemented vrgather or vcompress yet, but there are open pull request for them [0].
Sadly there also seem to be a few bugs when simulating with verilator [1], so I couldn't measure all instructions, but here is `vadd.vv` and `vwaddu.vv` for the VLEN=4096, four lane configuration:
vadd.vv:
e32m1: 16 cycles
e32m2 32 cycles
e32m4 63 cycles
e32m8 126 cycles
vwaddu.vv:
e32m1: 34 cycles
e32m2: 69 cycles
e32m4: 140 cycles
[0] https://github.com/pulp-platform/ara/pull/180
[1] https://github.com/pulp-platform/ara/issues/250
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432-Core Chiplet-Based RISC-V Chip Nearly Ready to Blast Into Space
The PULP Ara is a 64-bit Vector Unit
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I’m not expert, but I guess it is worth to check out
It's not made very clear until the Conclusion section that they have provided an open source implementation of a RVV 1.0 vector unit, available at https://github.com/pulp-platform/ara : "The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core."
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Yun, the first tape-out of CVA6 (Ariane) with Ara vector co-processor SoC manufactured
The source code of Ara as well as Ariane, also known as CVA6 is available on GitHub.
What are some alternatives?
XiangShan-doc - Documentation for XiangShan
cva6 - The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
XiangShan - Open-source high-performance RISC-V processor
simd_utils - A header only library implementing common mathematical functions using SIMD intrinsics
esp - Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy
snitch - ⛔ DEPRECATED ⛔ Lean but mean RISC-V system!
Unicorn Engine - Unicorn CPU emulator framework (ARM, AArch64, M68K, Mips, Sparc, PowerPC, RiscV, S390x, TriCore, X86)